Merge branch 'u-boot/master' into 'u-boot-arm/master'

9 files changed, 794 insertions, 171 deletions

diff --git a/arch/arm/cpu/armv7/omap-common/sata.c b/arch/arm/cpu/armv7/omap-common/sata.c
index cad4feed00..3b4dd3f5d7 100644
--- a/arch/arm/cpu/armv7/omap-common/sata.c
+++ b/arch/arm/cpu/armv7/omap-common/sata.c
@@ -70,7 +70,13 @@ int init_sata(int dev)
 	writel(val, TI_SATA_WRAPPER_BASE + TI_SATA_SYSCONFIG);
 
 	ret = ahci_init(DWC_AHSATA_BASE);
-	scsi_scan(1);
 
 	return ret;
 }
+
+/* On OMAP platforms SATA provides the SCSI subsystem */
+void scsi_init(void)
+{
+	init_sata(0);
+	scsi_scan(1);
+}
diff --git a/arch/arm/cpu/armv7/socfpga/Makefile b/arch/arm/cpu/armv7/socfpga/Makefile
index eb33f2c5fb..8b6e108c42 100644
--- a/arch/arm/cpu/armv7/socfpga/Makefile
+++ b/arch/arm/cpu/armv7/socfpga/Makefile
@@ -8,5 +8,6 @@
 #
 
 obj-y	:= lowlevel_init.o
-obj-y	+= misc.o timer.o reset_manager.o system_manager.o clock_manager.o
+obj-y	+= misc.o timer.o reset_manager.o system_manager.o clock_manager.o \
+	   fpga_manager.o
 obj-$(CONFIG_SPL_BUILD) += spl.o freeze_controller.o scan_manager.o
diff --git a/arch/arm/cpu/armv7/socfpga/clock_manager.c b/arch/arm/cpu/armv7/socfpga/clock_manager.c
index 158501acba..d869f47c88 100644
--- a/arch/arm/cpu/armv7/socfpga/clock_manager.c
+++ b/arch/arm/cpu/armv7/socfpga/clock_manager.c
@@ -8,38 +8,28 @@
 #include <asm/io.h>
 #include <asm/arch/clock_manager.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 static const struct socfpga_clock_manager *clock_manager_base =
-		(void *)SOCFPGA_CLKMGR_ADDRESS;
-
-#define CLKMGR_BYPASS_ENABLE	1
-#define CLKMGR_BYPASS_DISABLE	0
-#define CLKMGR_STAT_IDLE	0
-#define CLKMGR_STAT_BUSY	1
-#define CLKMGR_BYPASS_PERPLLSRC_SELECT_EOSC1		0
-#define CLKMGR_BYPASS_PERPLLSRC_SELECT_INPUT_MUX	1
-#define CLKMGR_BYPASS_SDRPLLSRC_SELECT_EOSC1		0
-#define CLKMGR_BYPASS_SDRPLLSRC_SELECT_INPUT_MUX	1
-
-#define CLEAR_BGP_EN_PWRDN \
-	(CLKMGR_MAINPLLGRP_VCO_PWRDN_SET(0)| \
-	CLKMGR_MAINPLLGRP_VCO_EN_SET(0)| \
-	CLKMGR_MAINPLLGRP_VCO_BGPWRDN_SET(0))
-
-#define VCO_EN_BASE \
-	(CLKMGR_MAINPLLGRP_VCO_PWRDN_SET(0)| \
-	CLKMGR_MAINPLLGRP_VCO_EN_SET(1)| \
-	CLKMGR_MAINPLLGRP_VCO_BGPWRDN_SET(0))
-
-static inline void cm_wait_for_lock(uint32_t mask)
+	(struct socfpga_clock_manager *)SOCFPGA_CLKMGR_ADDRESS;
+
+static void cm_wait_for_lock(uint32_t mask)
 {
 	register uint32_t inter_val;
+	uint32_t retry = 0;
 	do {
 		inter_val = readl(&clock_manager_base->inter) & mask;
-	} while (inter_val != mask);
+		if (inter_val == mask)
+			retry++;
+		else
+			retry = 0;
+		if (retry >= 10)
+			break;
+	} while (1);
 }
 
 /* function to poll in the fsm busy bit */
-static inline void cm_wait_for_fsm(void)
+static void cm_wait_for_fsm(void)
 {
 	while (readl(&clock_manager_base->stat) & CLKMGR_STAT_BUSY)
 		;
@@ -49,22 +39,22 @@ static inline void cm_wait_for_fsm(void)
  * function to write the bypass register which requires a poll of the
  * busy bit
  */
-static inline void cm_write_bypass(uint32_t val)
+static void cm_write_bypass(uint32_t val)
 {
 	writel(val, &clock_manager_base->bypass);
 	cm_wait_for_fsm();
 }
 
 /* function to write the ctrl register which requires a poll of the busy bit */
-static inline void cm_write_ctrl(uint32_t val)
+static void cm_write_ctrl(uint32_t val)
 {
 	writel(val, &clock_manager_base->ctrl);
 	cm_wait_for_fsm();
 }
 
 /* function to write a clock register that has phase information */
-static inline void cm_write_with_phase(uint32_t value,
-	uint32_t reg_address, uint32_t mask)
+static void cm_write_with_phase(uint32_t value,
+				uint32_t reg_address, uint32_t mask)
 {
 	/* poll until phase is zero */
 	while (readl(reg_address) & mask)
@@ -128,24 +118,18 @@ void cm_basic_init(const cm_config_t *cfg)
 	writel(0, &clock_manager_base->per_pll.en);
 
 	/* Put all plls in bypass */
-	cm_write_bypass(
-		CLKMGR_BYPASS_PERPLLSRC_SET(
-		CLKMGR_BYPASS_PERPLLSRC_SELECT_EOSC1) |
-		CLKMGR_BYPASS_SDRPLLSRC_SET(
-		CLKMGR_BYPASS_SDRPLLSRC_SELECT_EOSC1) |
-		CLKMGR_BYPASS_PERPLL_SET(CLKMGR_BYPASS_ENABLE) |
-		CLKMGR_BYPASS_SDRPLL_SET(CLKMGR_BYPASS_ENABLE) |
-		CLKMGR_BYPASS_MAINPLL_SET(CLKMGR_BYPASS_ENABLE));
+	cm_write_bypass(CLKMGR_BYPASS_PERPLL | CLKMGR_BYPASS_SDRPLL |
+			CLKMGR_BYPASS_MAINPLL);
 
-	/*
-	 * Put all plls VCO registers back to reset value.
-	 * Some code might have messed with them.
-	 */
-	writel(CLKMGR_MAINPLLGRP_VCO_RESET_VALUE,
+	/* Put all plls VCO registers back to reset value. */
+	writel(CLKMGR_MAINPLLGRP_VCO_RESET_VALUE &
+	       ~CLKMGR_MAINPLLGRP_VCO_REGEXTSEL_MASK,
 	       &clock_manager_base->main_pll.vco);
-	writel(CLKMGR_PERPLLGRP_VCO_RESET_VALUE,
+	writel(CLKMGR_PERPLLGRP_VCO_RESET_VALUE &
+	       ~CLKMGR_PERPLLGRP_VCO_REGEXTSEL_MASK,
 	       &clock_manager_base->per_pll.vco);
-	writel(CLKMGR_SDRPLLGRP_VCO_RESET_VALUE,
+	writel(CLKMGR_SDRPLLGRP_VCO_RESET_VALUE &
+	       ~CLKMGR_SDRPLLGRP_VCO_REGEXTSEL_MASK,
 	       &clock_manager_base->sdr_pll.vco);
 
 	/*
@@ -170,19 +154,9 @@ void cm_basic_init(const cm_config_t *cfg)
 	 * We made sure bgpwr down was assert for 5 us. Now deassert BG PWR DN
 	 * with numerator and denominator.
 	 */
-	writel(cfg->main_vco_base | CLEAR_BGP_EN_PWRDN |
-		CLKMGR_MAINPLLGRP_VCO_REGEXTSEL_MASK,
-		&clock_manager_base->main_pll.vco);
-
-	writel(cfg->peri_vco_base | CLEAR_BGP_EN_PWRDN |
-		CLKMGR_PERPLLGRP_VCO_REGEXTSEL_MASK,
-		&clock_manager_base->per_pll.vco);
-
-	writel(CLKMGR_SDRPLLGRP_VCO_OUTRESET_SET(0) |
-		CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_SET(0) |
-		cfg->sdram_vco_base | CLEAR_BGP_EN_PWRDN |
-		CLKMGR_SDRPLLGRP_VCO_REGEXTSEL_MASK,
-		&clock_manager_base->sdr_pll.vco);
+	writel(cfg->main_vco_base, &clock_manager_base->main_pll.vco);
+	writel(cfg->peri_vco_base, &clock_manager_base->per_pll.vco);
+	writel(cfg->sdram_vco_base, &clock_manager_base->sdr_pll.vco);
 
 	/*
 	 * Time starts here
@@ -217,6 +191,9 @@ void cm_basic_init(const cm_config_t *cfg)
 	writel(cfg->perqspiclk, &clock_manager_base->per_pll.perqspiclk);
 
 	/* Peri pernandsdmmcclk */
+	writel(cfg->mainnandsdmmcclk,
+	       &clock_manager_base->main_pll.mainnandsdmmcclk);
+
 	writel(cfg->pernandsdmmcclk,
 	       &clock_manager_base->per_pll.pernandsdmmcclk);
 
@@ -232,18 +209,16 @@ void cm_basic_init(const cm_config_t *cfg)
 
 	/* Enable vco */
 	/* main pll vco */
-	writel(cfg->main_vco_base | VCO_EN_BASE,
+	writel(cfg->main_vco_base | CLKMGR_MAINPLLGRP_VCO_EN,
 	       &clock_manager_base->main_pll.vco);
 
 	/* periferal pll */
-	writel(cfg->peri_vco_base | VCO_EN_BASE,
+	writel(cfg->peri_vco_base | CLKMGR_MAINPLLGRP_VCO_EN,
 	       &clock_manager_base->per_pll.vco);
 
 	/* sdram pll vco */
-	writel(CLKMGR_SDRPLLGRP_VCO_OUTRESET_SET(0) |
-		CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_SET(0) |
-		cfg->sdram_vco_base | VCO_EN_BASE,
-		&clock_manager_base->sdr_pll.vco);
+	writel(cfg->sdram_vco_base | CLKMGR_MAINPLLGRP_VCO_EN,
+	       &clock_manager_base->sdr_pll.vco);
 
 	/* L3 MP and L3 SP */
 	writel(cfg->maindiv, &clock_manager_base->main_pll.maindiv);
@@ -294,8 +269,8 @@ void cm_basic_init(const cm_config_t *cfg)
 	       &clock_manager_base->per_pll.vco);
 
 	/* assert sdram outresetall */
-	writel(cfg->sdram_vco_base | VCO_EN_BASE|
-		CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_SET(1),
+	writel(cfg->sdram_vco_base | CLKMGR_MAINPLLGRP_VCO_EN|
+		CLKMGR_SDRPLLGRP_VCO_OUTRESETALL,
 		&clock_manager_base->sdr_pll.vco);
 
 	/* deassert main outresetall */
@@ -307,9 +282,8 @@ void cm_basic_init(const cm_config_t *cfg)
 	       &clock_manager_base->per_pll.vco);
 
 	/* deassert sdram outresetall */
-	writel(CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_SET(0) |
-		cfg->sdram_vco_base | VCO_EN_BASE,
-		&clock_manager_base->sdr_pll.vco);
+	writel(cfg->sdram_vco_base | CLKMGR_MAINPLLGRP_VCO_EN,
+	       &clock_manager_base->sdr_pll.vco);
 
 	/*
 	 * now that we've toggled outreset all, all the clocks
@@ -333,18 +307,10 @@ void cm_basic_init(const cm_config_t *cfg)
 			    CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_MASK);
 
 	/* Take all three PLLs out of bypass when safe mode is cleared. */
-	cm_write_bypass(
-		CLKMGR_BYPASS_PERPLLSRC_SET(
-			CLKMGR_BYPASS_PERPLLSRC_SELECT_EOSC1) |
-		CLKMGR_BYPASS_SDRPLLSRC_SET(
-			CLKMGR_BYPASS_SDRPLLSRC_SELECT_EOSC1) |
-		CLKMGR_BYPASS_PERPLL_SET(CLKMGR_BYPASS_DISABLE) |
-		CLKMGR_BYPASS_SDRPLL_SET(CLKMGR_BYPASS_DISABLE) |
-		CLKMGR_BYPASS_MAINPLL_SET(CLKMGR_BYPASS_DISABLE));
+	cm_write_bypass(0);
 
 	/* clear safe mode */
-	cm_write_ctrl(readl(&clock_manager_base->ctrl) |
-			CLKMGR_CTRL_SAFEMODE_SET(CLKMGR_CTRL_SAFEMODE_MASK));
+	cm_write_ctrl(readl(&clock_manager_base->ctrl) | CLKMGR_CTRL_SAFEMODE);
 
 	/*
 	 * now that safe mode is clear with clocks gated
@@ -357,4 +323,224 @@ void cm_basic_init(const cm_config_t *cfg)
 	writel(~0, &clock_manager_base->main_pll.en);
 	writel(~0, &clock_manager_base->per_pll.en);
 	writel(~0, &clock_manager_base->sdr_pll.en);
+
+	/* Clear the loss of lock bits (write 1 to clear) */
+	writel(CLKMGR_INTER_SDRPLLLOST_MASK | CLKMGR_INTER_PERPLLLOST_MASK |
+	       CLKMGR_INTER_MAINPLLLOST_MASK,
+	       &clock_manager_base->inter);
+}
+
+static unsigned int cm_get_main_vco_clk_hz(void)
+{
+	uint32_t reg, clock;
+
+	/* get the main VCO clock */
+	reg = readl(&clock_manager_base->main_pll.vco);
+	clock = CONFIG_HPS_CLK_OSC1_HZ;
+	clock /= ((reg & CLKMGR_MAINPLLGRP_VCO_DENOM_MASK) >>
+		  CLKMGR_MAINPLLGRP_VCO_DENOM_OFFSET) + 1;
+	clock *= ((reg & CLKMGR_MAINPLLGRP_VCO_NUMER_MASK) >>
+		  CLKMGR_MAINPLLGRP_VCO_NUMER_OFFSET) + 1;
+
+	return clock;
+}
+
+static unsigned int cm_get_per_vco_clk_hz(void)
+{
+	uint32_t reg, clock = 0;
+
+	/* identify PER PLL clock source */
+	reg = readl(&clock_manager_base->per_pll.vco);
+	reg = (reg & CLKMGR_PERPLLGRP_VCO_SSRC_MASK) >>
+	      CLKMGR_PERPLLGRP_VCO_SSRC_OFFSET;
+	if (reg == CLKMGR_VCO_SSRC_EOSC1)
+		clock = CONFIG_HPS_CLK_OSC1_HZ;
+	else if (reg == CLKMGR_VCO_SSRC_EOSC2)
+		clock = CONFIG_HPS_CLK_OSC2_HZ;
+	else if (reg == CLKMGR_VCO_SSRC_F2S)
+		clock = CONFIG_HPS_CLK_F2S_PER_REF_HZ;
+
+	/* get the PER VCO clock */
+	reg = readl(&clock_manager_base->per_pll.vco);
+	clock /= ((reg & CLKMGR_PERPLLGRP_VCO_DENOM_MASK) >>
+		  CLKMGR_PERPLLGRP_VCO_DENOM_OFFSET) + 1;
+	clock *= ((reg & CLKMGR_PERPLLGRP_VCO_NUMER_MASK) >>
+		  CLKMGR_PERPLLGRP_VCO_NUMER_OFFSET) + 1;
+
+	return clock;
+}
+
+unsigned long cm_get_mpu_clk_hz(void)
+{
+	uint32_t reg, clock;
+
+	clock = cm_get_main_vco_clk_hz();
+
+	/* get the MPU clock */
+	reg = readl(&clock_manager_base->altera.mpuclk);
+	clock /= (reg + 1);
+	reg = readl(&clock_manager_base->main_pll.mpuclk);
+	clock /= (reg + 1);
+	return clock;
 }
+
+unsigned long cm_get_sdram_clk_hz(void)
+{
+	uint32_t reg, clock = 0;
+
+	/* identify SDRAM PLL clock source */
+	reg = readl(&clock_manager_base->sdr_pll.vco);
+	reg = (reg & CLKMGR_SDRPLLGRP_VCO_SSRC_MASK) >>
+	      CLKMGR_SDRPLLGRP_VCO_SSRC_OFFSET;
+	if (reg == CLKMGR_VCO_SSRC_EOSC1)
+		clock = CONFIG_HPS_CLK_OSC1_HZ;
+	else if (reg == CLKMGR_VCO_SSRC_EOSC2)
+		clock = CONFIG_HPS_CLK_OSC2_HZ;
+	else if (reg == CLKMGR_VCO_SSRC_F2S)
+		clock = CONFIG_HPS_CLK_F2S_SDR_REF_HZ;
+
+	/* get the SDRAM VCO clock */
+	reg = readl(&clock_manager_base->sdr_pll.vco);
+	clock /= ((reg & CLKMGR_SDRPLLGRP_VCO_DENOM_MASK) >>
+		  CLKMGR_SDRPLLGRP_VCO_DENOM_OFFSET) + 1;
+	clock *= ((reg & CLKMGR_SDRPLLGRP_VCO_NUMER_MASK) >>
+		  CLKMGR_SDRPLLGRP_VCO_NUMER_OFFSET) + 1;
+
+	/* get the SDRAM (DDR_DQS) clock */
+	reg = readl(&clock_manager_base->sdr_pll.ddrdqsclk);
+	reg = (reg & CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_MASK) >>
+	      CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_OFFSET;
+	clock /= (reg + 1);
+
+	return clock;
+}
+
+unsigned int cm_get_l4_sp_clk_hz(void)
+{
+	uint32_t reg, clock = 0;
+
+	/* identify the source of L4 SP clock */
+	reg = readl(&clock_manager_base->main_pll.l4src);
+	reg = (reg & CLKMGR_MAINPLLGRP_L4SRC_L4SP) >>
+	      CLKMGR_MAINPLLGRP_L4SRC_L4SP_OFFSET;
+
+	if (reg == CLKMGR_L4_SP_CLK_SRC_MAINPLL) {
+		clock = cm_get_main_vco_clk_hz();
+
+		/* get the clock prior L4 SP divider (main clk) */
+		reg = readl(&clock_manager_base->altera.mainclk);
+		clock /= (reg + 1);
+		reg = readl(&clock_manager_base->main_pll.mainclk);
+		clock /= (reg + 1);
+	} else if (reg == CLKMGR_L4_SP_CLK_SRC_PERPLL) {
+		clock = cm_get_per_vco_clk_hz();
+
+		/* get the clock prior L4 SP divider (periph_base_clk) */
+		reg = readl(&clock_manager_base->per_pll.perbaseclk);
+		clock /= (reg + 1);
+	}
+
+	/* get the L4 SP clock which supplied to UART */
+	reg = readl(&clock_manager_base->main_pll.maindiv);
+	reg = (reg & CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_MASK) >>
+	      CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_OFFSET;
+	clock = clock / (1 << reg);
+
+	return clock;
+}
+
+unsigned int cm_get_mmc_controller_clk_hz(void)
+{
+	uint32_t reg, clock = 0;
+
+	/* identify the source of MMC clock */
+	reg = readl(&clock_manager_base->per_pll.src);
+	reg = (reg & CLKMGR_PERPLLGRP_SRC_SDMMC_MASK) >>
+	      CLKMGR_PERPLLGRP_SRC_SDMMC_OFFSET;
+
+	if (reg == CLKMGR_SDMMC_CLK_SRC_F2S) {
+		clock = CONFIG_HPS_CLK_F2S_PER_REF_HZ;
+	} else if (reg == CLKMGR_SDMMC_CLK_SRC_MAIN) {
+		clock = cm_get_main_vco_clk_hz();
+
+		/* get the SDMMC clock */
+		reg = readl(&clock_manager_base->main_pll.mainnandsdmmcclk);
+		clock /= (reg + 1);
+	} else if (reg == CLKMGR_SDMMC_CLK_SRC_PER) {
+		clock = cm_get_per_vco_clk_hz();
+
+		/* get the SDMMC clock */
+		reg = readl(&clock_manager_base->per_pll.pernandsdmmcclk);
+		clock /= (reg + 1);
+	}
+
+	/* further divide by 4 as we have fixed divider at wrapper */
+	clock /= 4;
+	return clock;
+}
+
+unsigned int cm_get_qspi_controller_clk_hz(void)
+{
+	uint32_t reg, clock = 0;
+
+	/* identify the source of QSPI clock */
+	reg = readl(&clock_manager_base->per_pll.src);
+	reg = (reg & CLKMGR_PERPLLGRP_SRC_QSPI_MASK) >>
+	      CLKMGR_PERPLLGRP_SRC_QSPI_OFFSET;
+
+	if (reg == CLKMGR_QSPI_CLK_SRC_F2S) {
+		clock = CONFIG_HPS_CLK_F2S_PER_REF_HZ;
+	} else if (reg == CLKMGR_QSPI_CLK_SRC_MAIN) {
+		clock = cm_get_main_vco_clk_hz();
+
+		/* get the qspi clock */
+		reg = readl(&clock_manager_base->main_pll.mainqspiclk);
+		clock /= (reg + 1);
+	} else if (reg == CLKMGR_QSPI_CLK_SRC_PER) {
+		clock = cm_get_per_vco_clk_hz();
+
+		/* get the qspi clock */
+		reg = readl(&clock_manager_base->per_pll.perqspiclk);
+		clock /= (reg + 1);
+	}
+
+	return clock;
+}
+
+static void cm_print_clock_quick_summary(void)
+{
+	printf("MPU       %10ld kHz\n", cm_get_mpu_clk_hz() / 1000);
+	printf("DDR       %10ld kHz\n", cm_get_sdram_clk_hz() / 1000);
+	printf("EOSC1       %8d kHz\n", CONFIG_HPS_CLK_OSC1_HZ / 1000);
+	printf("EOSC2       %8d kHz\n", CONFIG_HPS_CLK_OSC2_HZ / 1000);
+	printf("F2S_SDR_REF %8d kHz\n", CONFIG_HPS_CLK_F2S_SDR_REF_HZ / 1000);
+	printf("F2S_PER_REF %8d kHz\n", CONFIG_HPS_CLK_F2S_PER_REF_HZ / 1000);
+	printf("MMC         %8d kHz\n", cm_get_mmc_controller_clk_hz() / 1000);
+	printf("QSPI        %8d kHz\n", cm_get_qspi_controller_clk_hz() / 1000);
+	printf("UART        %8d kHz\n", cm_get_l4_sp_clk_hz() / 1000);
+}
+
+int set_cpu_clk_info(void)
+{
+	/* Calculate the clock frequencies required for drivers */
+	cm_get_l4_sp_clk_hz();
+	cm_get_mmc_controller_clk_hz();
+
+	gd->bd->bi_arm_freq = cm_get_mpu_clk_hz() / 1000000;
+	gd->bd->bi_dsp_freq = 0;
+	gd->bd->bi_ddr_freq = cm_get_sdram_clk_hz() / 1000000;
+
+	return 0;
+}
+
+int do_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	cm_print_clock_quick_summary();
+	return 0;
+}
+
+U_BOOT_CMD(
+	clocks,	CONFIG_SYS_MAXARGS, 1, do_showclocks,
+	"display clocks",
+	""
+);
diff --git a/arch/arm/cpu/armv7/socfpga/fpga_manager.c b/arch/arm/cpu/armv7/socfpga/fpga_manager.c
new file mode 100644
index 0000000000..43fd2fedee
--- /dev/null
+++ b/arch/arm/cpu/armv7/socfpga/fpga_manager.c
@@ -0,0 +1,78 @@
+/*
+ * Copyright (C) 2012 Altera Corporation <www.altera.com>
+ * All rights reserved.
+ *
+ * This file contains only support functions used also by the SoCFPGA
+ * platform code, the real meat is located in drivers/fpga/socfpga.c .
+ *
+ * SPDX-License-Identifier:	BSD-3-Clause
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/errno.h>
+#include <asm/arch/fpga_manager.h>
+#include <asm/arch/reset_manager.h>
+#include <asm/arch/system_manager.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* Timeout count */
+#define FPGA_TIMEOUT_CNT		0x1000000
+
+static struct socfpga_fpga_manager *fpgamgr_regs =
+	(struct socfpga_fpga_manager *)SOCFPGA_FPGAMGRREGS_ADDRESS;
+
+/* Check whether FPGA Init_Done signal is high */
+static int is_fpgamgr_initdone_high(void)
+{
+	unsigned long val;
+
+	val = readl(&fpgamgr_regs->gpio_ext_porta);
+	return val & FPGAMGRREGS_MON_GPIO_EXT_PORTA_ID_MASK;
+}
+
+/* Get the FPGA mode */
+int fpgamgr_get_mode(void)
+{
+	unsigned long val;
+
+	val = readl(&fpgamgr_regs->stat);
+	return val & FPGAMGRREGS_STAT_MODE_MASK;
+}
+
+/* Check whether FPGA is ready to be accessed */
+int fpgamgr_test_fpga_ready(void)
+{
+	/* Check for init done signal */
+	if (!is_fpgamgr_initdone_high())
+		return 0;
+
+	/* Check again to avoid false glitches */
+	if (!is_fpgamgr_initdone_high())
+		return 0;
+
+	if (fpgamgr_get_mode() != FPGAMGRREGS_MODE_USERMODE)
+		return 0;
+
+	return 1;
+}
+
+/* Poll until FPGA is ready to be accessed or timeout occurred */
+int fpgamgr_poll_fpga_ready(void)
+{
+	unsigned long i;
+
+	/* If FPGA is blank, wait till WD invoke warm reset */
+	for (i = 0; i < FPGA_TIMEOUT_CNT; i++) {
+		/* check for init done signal */
+		if (!is_fpgamgr_initdone_high())
+			continue;
+		/* check again to avoid false glitches */
+		if (!is_fpgamgr_initdone_high())
+			continue;
+		return 1;
+	}
+
+	return 0;
+}
diff --git a/arch/arm/cpu/armv7/socfpga/misc.c b/arch/arm/cpu/armv7/socfpga/misc.c
index ecae393410..0eab264668 100644
--- a/arch/arm/cpu/armv7/socfpga/misc.c
+++ b/arch/arm/cpu/armv7/socfpga/misc.c
@@ -6,24 +6,103 @@
 
 #include <common.h>
 #include <asm/io.h>
+#include <altera.h>
 #include <miiphy.h>
 #include <netdev.h>
+#include <asm/arch/reset_manager.h>
+#include <asm/arch/system_manager.h>
+#include <asm/arch/dwmmc.h>
+#include <asm/arch/nic301.h>
+#include <asm/arch/scu.h>
+#include <asm/pl310.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
+static struct pl310_regs *const pl310 =
+	(struct pl310_regs *)CONFIG_SYS_PL310_BASE;
+static struct socfpga_system_manager *sysmgr_regs =
+	(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
+static struct socfpga_reset_manager *reset_manager_base =
+	(struct socfpga_reset_manager *)SOCFPGA_RSTMGR_ADDRESS;
+static struct nic301_registers *nic301_regs =
+	(struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS;
+static struct scu_registers *scu_regs =
+	(struct scu_registers *)SOCFPGA_MPUSCU_ADDRESS;
+
 int dram_init(void)
 {
 	gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
 	return 0;
 }
 
+void enable_caches(void)
+{
+#ifndef CONFIG_SYS_ICACHE_OFF
+	icache_enable();
+#endif
+#ifndef CONFIG_SYS_DCACHE_OFF
+	dcache_enable();
+#endif
+}
+
+/*
+ * DesignWare Ethernet initialization
+ */
+#ifdef CONFIG_DESIGNWARE_ETH
+int cpu_eth_init(bd_t *bis)
+{
+#if CONFIG_EMAC_BASE == SOCFPGA_EMAC0_ADDRESS
+	const int physhift = SYSMGR_EMACGRP_CTRL_PHYSEL0_LSB;
+#elif CONFIG_EMAC_BASE == SOCFPGA_EMAC1_ADDRESS
+	const int physhift = SYSMGR_EMACGRP_CTRL_PHYSEL1_LSB;
+#else
+#error "Incorrect CONFIG_EMAC_BASE value!"
+#endif
+
+	/* Initialize EMAC. This needs to be done at least once per boot. */
+
+	/*
+	 * Putting the EMAC controller to reset when configuring the PHY
+	 * interface select at System Manager
+	 */
+	socfpga_emac_reset(1);
+
+	/* Clearing emac0 PHY interface select to 0 */
+	clrbits_le32(&sysmgr_regs->emacgrp_ctrl,
+		     SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << physhift);
+
+	/* configure to PHY interface select choosed */
+	setbits_le32(&sysmgr_regs->emacgrp_ctrl,
+		     SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII << physhift);
+
+	/* Release the EMAC controller from reset */
+	socfpga_emac_reset(0);
+
+	/* initialize and register the emac */
+	return designware_initialize(CONFIG_EMAC_BASE,
+				     CONFIG_PHY_INTERFACE_MODE);
+}
+#endif
+
+#ifdef CONFIG_DWMMC
+/*
+ * Initializes MMC controllers.
+ * to override, implement board_mmc_init()
+ */
+int cpu_mmc_init(bd_t *bis)
+{
+	return socfpga_dwmmc_init(SOCFPGA_SDMMC_ADDRESS,
+				  CONFIG_HPS_SDMMC_BUSWIDTH, 0);
+}
+#endif
+
 #if defined(CONFIG_DISPLAY_CPUINFO)
 /*
  * Print CPU information
  */
 int print_cpuinfo(void)
 {
-	puts("CPU   : Altera SOCFPGA Platform\n");
+	puts("CPU:   Altera SoCFPGA Platform\n");
 	return 0;
 }
 #endif
@@ -36,22 +115,159 @@ int overwrite_console(void)
 }
 #endif
 
-int misc_init_r(void)
+#ifdef CONFIG_FPGA
+/*
+ * FPGA programming support for SoC FPGA Cyclone V
+ */
+static Altera_desc altera_fpga[] = {
+	{
+		/* Family */
+		Altera_SoCFPGA,
+		/* Interface type */
+		fast_passive_parallel,
+		/* No limitation as additional data will be ignored */
+		-1,
+		/* No device function table */
+		NULL,
+		/* Base interface address specified in driver */
+		NULL,
+		/* No cookie implementation */
+		0
+	},
+};
+
+/* add device descriptor to FPGA device table */
+static void socfpga_fpga_add(void)
 {
-	return 0;
+	int i;
+	fpga_init();
+	for (i = 0; i < ARRAY_SIZE(altera_fpga); i++)
+		fpga_add(fpga_altera, &altera_fpga[i]);
 }
+#else
+static inline void socfpga_fpga_add(void) {}
+#endif
 
+int arch_cpu_init(void)
+{
+	/*
+	 * If the HW watchdog is NOT enabled, make sure it is not running,
+	 * for example because it was enabled in the preloader. This might
+	 * trigger a watchdog-triggered reboot of Linux kernel later.
+	 */
+#ifndef CONFIG_HW_WATCHDOG
+	socfpga_watchdog_reset();
+#endif
+	return 0;
+}
 
 /*
- * DesignWare Ethernet initialization
+ * Convert all NIC-301 AMBA slaves from secure to non-secure
  */
-int cpu_eth_init(bd_t *bis)
+static void socfpga_nic301_slave_ns(void)
 {
-#if !defined(CONFIG_SOCFPGA_VIRTUAL_TARGET) && !defined(CONFIG_SPL_BUILD)
-       /* initialize and register the emac */
-	return designware_initialize(CONFIG_EMAC_BASE,
-				     CONFIG_PHY_INTERFACE_MODE);
+	writel(0x1, &nic301_regs->lwhps2fpgaregs);
+	writel(0x1, &nic301_regs->hps2fpgaregs);
+	writel(0x1, &nic301_regs->acp);
+	writel(0x1, &nic301_regs->rom);
+	writel(0x1, &nic301_regs->ocram);
+	writel(0x1, &nic301_regs->sdrdata);
+}
+
+static uint32_t iswgrp_handoff[8];
+
+int misc_init_r(void)
+{
+	int i;
+	for (i = 0; i < 8; i++)	/* Cache initial SW setting regs */
+		iswgrp_handoff[i] = readl(&sysmgr_regs->iswgrp_handoff[i]);
+
+	socfpga_bridges_reset(1);
+	socfpga_nic301_slave_ns();
+
+	/*
+	 * Private components security:
+	 * U-Boot : configure private timer, global timer and cpu component
+	 * access as non secure for kernel stage (as required by Linux)
+	 */
+	setbits_le32(&scu_regs->sacr, 0xfff);
+
+	/* Configure the L2 controller to make SDRAM start at 0 */
+#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
+	writel(0x2, &nic301_regs->remap);
 #else
-	return 0;
+	writel(0x1, &nic301_regs->remap);	/* remap.mpuzero */
+	writel(0x1, &pl310->pl310_addr_filter_start);
 #endif
+
+	/* Add device descriptor to FPGA device table */
+	socfpga_fpga_add();
+	return 0;
+}
+
+static void socfpga_sdram_apply_static_cfg(void)
+{
+	const uint32_t staticcfg = SOCFPGA_SDR_ADDRESS + 0x505c;
+	const uint32_t applymask = 0x8;
+	uint32_t val = readl(staticcfg) | applymask;
+
+	/*
+	 * SDRAM staticcfg register specific:
+	 * When applying the register setting, the CPU must not access
+	 * SDRAM. Luckily for us, we can abuse i-cache here to help us
+	 * circumvent the SDRAM access issue. The idea is to make sure
+	 * that the code is in one full i-cache line by branching past
+	 * it and back. Once it is in the i-cache, we execute the core
+	 * of the code and apply the register settings.
+	 *
+	 * The code below uses 7 instructions, while the Cortex-A9 has
+	 * 32-byte cachelines, thus the limit is 8 instructions total.
+	 */
+	asm volatile(
+		".align	5			\n"
+		"	b	2f		\n"
+		"1:	str	%0,	[%1]	\n"
+		"	dsb			\n"
+		"	isb			\n"
+		"	b	3f		\n"
+		"2:	b	1b		\n"
+		"3:	nop			\n"
+	: : "r"(val), "r"(staticcfg) : "memory", "cc");
 }
+
+int do_bridge(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	if (argc != 2)
+		return CMD_RET_USAGE;
+
+	argv++;
+
+	switch (*argv[0]) {
+	case 'e':	/* Enable */
+		writel(iswgrp_handoff[2], &sysmgr_regs->fpgaintfgrp_module);
+		socfpga_sdram_apply_static_cfg();
+		writel(iswgrp_handoff[3], SOCFPGA_SDR_ADDRESS + 0x5080);
+		writel(iswgrp_handoff[0], &reset_manager_base->brg_mod_reset);
+		writel(iswgrp_handoff[1], &nic301_regs->remap);
+		break;
+	case 'd':	/* Disable */
+		writel(0, &sysmgr_regs->fpgaintfgrp_module);
+		writel(0, SOCFPGA_SDR_ADDRESS + 0x5080);
+		socfpga_sdram_apply_static_cfg();
+		writel(0, &reset_manager_base->brg_mod_reset);
+		writel(1, &nic301_regs->remap);
+		break;
+	default:
+		return CMD_RET_USAGE;
+	}
+
+	return 0;
+}
+
+U_BOOT_CMD(
+	bridge, 2, 1, do_bridge,
+	"SoCFPGA HPS FPGA bridge control",
+	"enable  - Enable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA bridges\n"
+	"bridge disable - Enable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA bridges\n"
+	""
+);
diff --git a/arch/arm/cpu/armv7/socfpga/reset_manager.c b/arch/arm/cpu/armv7/socfpga/reset_manager.c
index e320c011ae..1d3a95d0c8 100644
--- a/arch/arm/cpu/armv7/socfpga/reset_manager.c
+++ b/arch/arm/cpu/armv7/socfpga/reset_manager.c
@@ -8,12 +8,25 @@
 #include <common.h>
 #include <asm/io.h>
 #include <asm/arch/reset_manager.h>
+#include <asm/arch/fpga_manager.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
 static const struct socfpga_reset_manager *reset_manager_base =
 		(void *)SOCFPGA_RSTMGR_ADDRESS;
 
+/* Toggle reset signal to watchdog (WDT is disabled after this operation!) */
+void socfpga_watchdog_reset(void)
+{
+	/* assert reset for watchdog */
+	setbits_le32(&reset_manager_base->per_mod_reset,
+		     1 << RSTMGR_PERMODRST_L4WD0_LSB);
+
+	/* deassert watchdog from reset (watchdog in not running state) */
+	clrbits_le32(&reset_manager_base->per_mod_reset,
+		     1 << RSTMGR_PERMODRST_L4WD0_LSB);
+}
+
 /*
  * Write the reset manager register to cause reset
  */
@@ -37,3 +50,57 @@ void reset_deassert_peripherals_handoff(void)
 {
 	writel(0, &reset_manager_base->per_mod_reset);
 }
+
+#if defined(CONFIG_SOCFPGA_VIRTUAL_TARGET)
+void socfpga_bridges_reset(int enable)
+{
+	/* For SoCFPGA-VT, this is NOP. */
+}
+#else
+
+#define L3REGS_REMAP_LWHPS2FPGA_MASK	0x10
+#define L3REGS_REMAP_HPS2FPGA_MASK	0x08
+#define L3REGS_REMAP_OCRAM_MASK		0x01
+
+void socfpga_bridges_reset(int enable)
+{
+	const uint32_t l3mask = L3REGS_REMAP_LWHPS2FPGA_MASK |
+				L3REGS_REMAP_HPS2FPGA_MASK |
+				L3REGS_REMAP_OCRAM_MASK;
+
+	if (enable) {
+		/* brdmodrst */
+		writel(0xffffffff, &reset_manager_base->brg_mod_reset);
+	} else {
+		/* Check signal from FPGA. */
+		if (fpgamgr_poll_fpga_ready()) {
+			/* FPGA not ready. Wait for watchdog timeout. */
+			printf("%s: fpga not ready, hanging.\n", __func__);
+			hang();
+		}
+
+		/* brdmodrst */
+		writel(0, &reset_manager_base->brg_mod_reset);
+
+		/* Remap the bridges into memory map */
+		writel(l3mask, SOCFPGA_L3REGS_ADDRESS);
+	}
+}
+#endif
+
+/* Change the reset state for EMAC 0 and EMAC 1 */
+void socfpga_emac_reset(int enable)
+{
+	const void *reset = &reset_manager_base->per_mod_reset;
+
+	if (enable) {
+		setbits_le32(reset, 1 << RSTMGR_PERMODRST_EMAC0_LSB);
+		setbits_le32(reset, 1 << RSTMGR_PERMODRST_EMAC1_LSB);
+	} else {
+#if (CONFIG_EMAC_BASE == SOCFPGA_EMAC0_ADDRESS)
+		clrbits_le32(reset, 1 << RSTMGR_PERMODRST_EMAC0_LSB);
+#elif (CONFIG_EMAC_BASE == SOCFPGA_EMAC1_ADDRESS)
+		clrbits_le32(reset, 1 << RSTMGR_PERMODRST_EMAC1_LSB);
+#endif
+	}
+}
diff --git a/arch/arm/cpu/armv7/socfpga/spl.c b/arch/arm/cpu/armv7/socfpga/spl.c
index 27efde62cc..bd9f338301 100644
--- a/arch/arm/cpu/armv7/socfpga/spl.c
+++ b/arch/arm/cpu/armv7/socfpga/spl.c
@@ -19,6 +19,31 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+#define MAIN_VCO_BASE (					\
+	(CONFIG_HPS_MAINPLLGRP_VCO_DENOM <<		\
+		CLKMGR_MAINPLLGRP_VCO_DENOM_OFFSET) |	\
+	(CONFIG_HPS_MAINPLLGRP_VCO_NUMER <<		\
+		CLKMGR_MAINPLLGRP_VCO_NUMER_OFFSET)	\
+	)
+
+#define PERI_VCO_BASE (					\
+	(CONFIG_HPS_PERPLLGRP_VCO_PSRC <<		\
+		CLKMGR_PERPLLGRP_VCO_PSRC_OFFSET) |	\
+	(CONFIG_HPS_PERPLLGRP_VCO_DENOM <<		\
+		CLKMGR_PERPLLGRP_VCO_DENOM_OFFSET) |	\
+	(CONFIG_HPS_PERPLLGRP_VCO_NUMER <<		\
+		CLKMGR_PERPLLGRP_VCO_NUMER_OFFSET)	\
+	)
+
+#define SDR_VCO_BASE (					\
+	(CONFIG_HPS_SDRPLLGRP_VCO_SSRC <<		\
+		CLKMGR_SDRPLLGRP_VCO_SSRC_OFFSET) |	\
+	(CONFIG_HPS_SDRPLLGRP_VCO_DENOM <<		\
+		CLKMGR_SDRPLLGRP_VCO_DENOM_OFFSET) |	\
+	(CONFIG_HPS_SDRPLLGRP_VCO_NUMER <<		\
+		CLKMGR_SDRPLLGRP_VCO_NUMER_OFFSET)	\
+	)
+
 u32 spl_boot_device(void)
 {
 	return BOOT_DEVICE_RAM;
@@ -33,86 +58,87 @@ void spl_board_init(void)
 	cm_config_t cm_default_cfg = {
 		/* main group */
 		MAIN_VCO_BASE,
-		CLKMGR_MAINPLLGRP_MPUCLK_CNT_SET(
-			CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT),
-		CLKMGR_MAINPLLGRP_MAINCLK_CNT_SET(
-			CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT),
-		CLKMGR_MAINPLLGRP_DBGATCLK_CNT_SET(
-			CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT),
-		CLKMGR_MAINPLLGRP_MAINQSPICLK_CNT_SET(
-			CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT),
-		CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_SET(
-			CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT),
-		CLKMGR_MAINPLLGRP_CFGS2FUSER0CLK_CNT_SET(
-			CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT),
-		CLKMGR_MAINPLLGRP_MAINDIV_L3MPCLK_SET(
-			CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK) |
-		CLKMGR_MAINPLLGRP_MAINDIV_L3SPCLK_SET(
-			CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK) |
-		CLKMGR_MAINPLLGRP_MAINDIV_L4MPCLK_SET(
-			CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK) |
-		CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_SET(
-			CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK),
-		CLKMGR_MAINPLLGRP_DBGDIV_DBGATCLK_SET(
-			CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK) |
-		CLKMGR_MAINPLLGRP_DBGDIV_DBGCLK_SET(
-			CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK),
-		CLKMGR_MAINPLLGRP_TRACEDIV_TRACECLK_SET(
-			CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK),
-		CLKMGR_MAINPLLGRP_L4SRC_L4MP_SET(
-			CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP) |
-		CLKMGR_MAINPLLGRP_L4SRC_L4SP_SET(
-			CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP),
+		(CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT <<
+			CLKMGR_MAINPLLGRP_MPUCLK_CNT_OFFSET),
+		(CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT <<
+			CLKMGR_MAINPLLGRP_MAINCLK_CNT_OFFSET),
+		(CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT <<
+			CLKMGR_MAINPLLGRP_DBGATCLK_CNT_OFFSET),
+		(CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT <<
+			CLKMGR_MAINPLLGRP_MAINQSPICLK_CNT_OFFSET),
+		(CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT <<
+			CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_OFFSET),
+		(CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT <<
+			CLKMGR_MAINPLLGRP_CFGS2FUSER0CLK_CNT_OFFSET),
+		(CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK <<
+			CLKMGR_MAINPLLGRP_MAINDIV_L3MPCLK_OFFSET) |
+		(CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK <<
+			CLKMGR_MAINPLLGRP_MAINDIV_L3SPCLK_OFFSET) |
+		(CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK <<
+			CLKMGR_MAINPLLGRP_MAINDIV_L4MPCLK_OFFSET) |
+		(CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK <<
+			CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_OFFSET),
+		(CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK <<
+			CLKMGR_MAINPLLGRP_DBGDIV_DBGATCLK_OFFSET) |
+		(CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK <<
+			CLKMGR_MAINPLLGRP_DBGDIV_DBGCLK_OFFSET),
+		(CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK <<
+			CLKMGR_MAINPLLGRP_TRACEDIV_TRACECLK_OFFSET),
+		(CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP <<
+			CLKMGR_MAINPLLGRP_L4SRC_L4MP_OFFSET) |
+		(CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP <<
+			CLKMGR_MAINPLLGRP_L4SRC_L4SP_OFFSET),
 
 		/* peripheral group */
 		PERI_VCO_BASE,
-		CLKMGR_PERPLLGRP_EMAC0CLK_CNT_SET(
-			CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT),
-		CLKMGR_PERPLLGRP_EMAC1CLK_CNT_SET(
-			CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT),
-		CLKMGR_PERPLLGRP_PERQSPICLK_CNT_SET(
-			CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT),
-		CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_SET(
-			CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT),
-		CLKMGR_PERPLLGRP_PERBASECLK_CNT_SET(
-			CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT),
-		CLKMGR_PERPLLGRP_S2FUSER1CLK_CNT_SET(
-			CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT),
-		CLKMGR_PERPLLGRP_DIV_USBCLK_SET(
-			CONFIG_HPS_PERPLLGRP_DIV_USBCLK) |
-		CLKMGR_PERPLLGRP_DIV_SPIMCLK_SET(
-			CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK) |
-		CLKMGR_PERPLLGRP_DIV_CAN0CLK_SET(
-			CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK) |
-		CLKMGR_PERPLLGRP_DIV_CAN1CLK_SET(
-			CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK),
-		CLKMGR_PERPLLGRP_GPIODIV_GPIODBCLK_SET(
-			CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK),
-		CLKMGR_PERPLLGRP_SRC_QSPI_SET(
-			CONFIG_HPS_PERPLLGRP_SRC_QSPI) |
-		CLKMGR_PERPLLGRP_SRC_NAND_SET(
-			CONFIG_HPS_PERPLLGRP_SRC_NAND) |
-		CLKMGR_PERPLLGRP_SRC_SDMMC_SET(
-			CONFIG_HPS_PERPLLGRP_SRC_SDMMC),
+		(CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT <<
+			CLKMGR_PERPLLGRP_EMAC0CLK_CNT_OFFSET),
+		(CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT <<
+			CLKMGR_PERPLLGRP_EMAC1CLK_CNT_OFFSET),
+		(CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT <<
+			CLKMGR_PERPLLGRP_PERQSPICLK_CNT_OFFSET),
+		(CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT <<
+			CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_OFFSET),
+		(CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT <<
+			CLKMGR_PERPLLGRP_PERBASECLK_CNT_OFFSET),
+		(CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT <<
+			CLKMGR_PERPLLGRP_S2FUSER1CLK_CNT_OFFSET),
+		(CONFIG_HPS_PERPLLGRP_DIV_USBCLK <<
+			CLKMGR_PERPLLGRP_DIV_USBCLK_OFFSET) |
+		(CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK <<
+			CLKMGR_PERPLLGRP_DIV_SPIMCLK_OFFSET) |
+		(CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK <<
+			CLKMGR_PERPLLGRP_DIV_CAN0CLK_OFFSET) |
+		(CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK <<
+			CLKMGR_PERPLLGRP_DIV_CAN1CLK_OFFSET),
+		(CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK <<
+			CLKMGR_PERPLLGRP_GPIODIV_GPIODBCLK_OFFSET),
+		(CONFIG_HPS_PERPLLGRP_SRC_QSPI <<
+			CLKMGR_PERPLLGRP_SRC_QSPI_OFFSET) |
+		(CONFIG_HPS_PERPLLGRP_SRC_NAND <<
+			CLKMGR_PERPLLGRP_SRC_NAND_OFFSET) |
+		(CONFIG_HPS_PERPLLGRP_SRC_SDMMC <<
+			CLKMGR_PERPLLGRP_SRC_SDMMC_OFFSET),
 
 		/* sdram pll group */
 		SDR_VCO_BASE,
-		CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_SET(
-			CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE) |
-		CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_SET(
-			CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT),
-		CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_SET(
-			CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE) |
-		CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_SET(
-			CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT),
-		CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_SET(
-			CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE) |
-		CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_SET(
-			CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT),
-		CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_SET(
-			CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE) |
-		CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_SET(
-			CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT),
+		(CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE <<
+			CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_OFFSET) |
+		(CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT <<
+			CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_OFFSET),
+		(CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE <<
+			CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_OFFSET) |
+		(CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT <<
+			CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_OFFSET),
+		(CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE <<
+			CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_OFFSET) |
+		(CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT <<
+			CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_OFFSET),
+		(CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE <<
+			CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_OFFSET) |
+		(CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT <<
+			CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_OFFSET),
+
 	};
 
 	debug("Freezing all I/O banks\n");
diff --git a/arch/arm/cpu/armv7/socfpga/system_manager.c b/arch/arm/cpu/armv7/socfpga/system_manager.c
index d96521ba03..11f7badbf2 100644
--- a/arch/arm/cpu/armv7/socfpga/system_manager.c
+++ b/arch/arm/cpu/armv7/socfpga/system_manager.c
@@ -1,5 +1,5 @@
 /*
- *  Copyright (C) 2013 Altera Corporation <www.altera.com>
+ * Copyright (C) 2013 Altera Corporation <www.altera.com>
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
@@ -7,21 +7,62 @@
 #include <common.h>
 #include <asm/io.h>
 #include <asm/arch/system_manager.h>
+#include <asm/arch/fpga_manager.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
+static struct socfpga_system_manager *sysmgr_regs =
+	(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
+
+/*
+ * Populate the value for SYSMGR.FPGAINTF.MODULE based on pinmux setting.
+ * The value is not wrote to SYSMGR.FPGAINTF.MODULE but
+ * CONFIG_SYSMGR_ISWGRP_HANDOFF.
+ */
+static void populate_sysmgr_fpgaintf_module(void)
+{
+	uint32_t handoff_val = 0;
+
+	/* ISWGRP_HANDOFF_FPGAINTF */
+	writel(0, &sysmgr_regs->iswgrp_handoff[2]);
+
+	/* Enable the signal for those HPS peripherals that use FPGA. */
+	if (readl(&sysmgr_regs->nandusefpga) == SYSMGR_FPGAINTF_USEFPGA)
+		handoff_val |= SYSMGR_FPGAINTF_NAND;
+	if (readl(&sysmgr_regs->rgmii1usefpga) == SYSMGR_FPGAINTF_USEFPGA)
+		handoff_val |= SYSMGR_FPGAINTF_EMAC1;
+	if (readl(&sysmgr_regs->sdmmcusefpga) == SYSMGR_FPGAINTF_USEFPGA)
+		handoff_val |= SYSMGR_FPGAINTF_SDMMC;
+	if (readl(&sysmgr_regs->rgmii0usefpga) == SYSMGR_FPGAINTF_USEFPGA)
+		handoff_val |= SYSMGR_FPGAINTF_EMAC0;
+	if (readl(&sysmgr_regs->spim0usefpga) == SYSMGR_FPGAINTF_USEFPGA)
+		handoff_val |= SYSMGR_FPGAINTF_SPIM0;
+	if (readl(&sysmgr_regs->spim1usefpga) == SYSMGR_FPGAINTF_USEFPGA)
+		handoff_val |= SYSMGR_FPGAINTF_SPIM1;
+
+	/* populate (not writing) the value for SYSMGR.FPGAINTF.MODULE
+	based on pinmux setting */
+	setbits_le32(&sysmgr_regs->iswgrp_handoff[2], handoff_val);
+
+	handoff_val = readl(&sysmgr_regs->iswgrp_handoff[2]);
+	if (fpgamgr_test_fpga_ready()) {
+		/* Enable the required signals only */
+		writel(handoff_val, &sysmgr_regs->fpgaintfgrp_module);
+	}
+}
+
 /*
  * Configure all the pin muxes
  */
 void sysmgr_pinmux_init(void)
 {
-	unsigned long offset = CONFIG_SYSMGR_PINMUXGRP_OFFSET;
-
-	const unsigned long *pval = sys_mgr_init_table;
-	unsigned long i;
+	uint32_t regs = (uint32_t)&sysmgr_regs->emacio[0];
+	int i;
 
-	for (i = 0; i < ARRAY_SIZE(sys_mgr_init_table);
-		i++, offset += sizeof(unsigned long)) {
-		writel(*pval++, (SOCFPGA_SYSMGR_ADDRESS + offset));
+	for (i = 0; i < ARRAY_SIZE(sys_mgr_init_table); i++) {
+		writel(sys_mgr_init_table[i], regs);
+		regs += sizeof(regs);
 	}
+
+	populate_sysmgr_fpgaintf_module();
 }
diff --git a/arch/arm/cpu/armv7/socfpga/timer.c b/arch/arm/cpu/armv7/socfpga/timer.c
index 58fc789e64..253cde39d1 100644
--- a/arch/arm/cpu/armv7/socfpga/timer.c
+++ b/arch/arm/cpu/armv7/socfpga/timer.c
@@ -8,6 +8,8 @@
 #include <asm/io.h>
 #include <asm/arch/timer.h>
 
+#define TIMER_LOAD_VAL		0xFFFFFFFF
+
 static const struct socfpga_timer *timer_base = (void *)CONFIG_SYS_TIMERBASE;
 
 /*