Merge branch 'master' of http://git.denx.de/u-boot-sunxi

7 files changed, 92 insertions, 16 deletions

diff --git a/arch/arm/cpu/armv7/sunxi/Makefile b/arch/arm/cpu/armv7/sunxi/Makefile
index dfb0a3e3c0..ce8e5717e7 100644
--- a/arch/arm/cpu/armv7/sunxi/Makefile
+++ b/arch/arm/cpu/armv7/sunxi/Makefile
@@ -33,6 +33,7 @@ obj-$(CONFIG_MACH_SUN8I)	+= clock_sun6i.o
 endif
 obj-$(CONFIG_MACH_SUN9I)	+= clock_sun9i.o
 obj-$(CONFIG_MACH_SUN6I)	+= tzpc.o
+obj-$(CONFIG_MACH_SUN8I_H3)	+= tzpc.o
 
 obj-$(CONFIG_AXP152_POWER)	+= pmic_bus.o
 obj-$(CONFIG_AXP209_POWER)	+= pmic_bus.o
diff --git a/arch/arm/cpu/armv7/sunxi/board.c b/arch/arm/cpu/armv7/sunxi/board.c
index 7dfb7f5340..eb5f4b686e 100644
--- a/arch/arm/cpu/armv7/sunxi/board.c
+++ b/arch/arm/cpu/armv7/sunxi/board.c
@@ -127,8 +127,8 @@ void s_init(void)
 		"orr r0, r0, #1 << 6\n"
 		"mcr p15, 0, r0, c1, c0, 1\n");
 #endif
-#if defined CONFIG_MACH_SUN6I
-	/* Enable non-secure access to the RTC */
+#if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I_H3
+	/* Enable non-secure access to some peripherals */
 	tzpc_init();
 #endif
 
diff --git a/arch/arm/cpu/armv7/sunxi/clock.c b/arch/arm/cpu/armv7/sunxi/clock.c
index 47fb70ff7c..5cc5d25d2b 100644
--- a/arch/arm/cpu/armv7/sunxi/clock.c
+++ b/arch/arm/cpu/armv7/sunxi/clock.c
@@ -14,12 +14,17 @@
 #include <asm/arch/gpio.h>
 #include <asm/arch/sys_proto.h>
 
+__weak void clock_init_sec(void)
+{
+}
+
 int clock_init(void)
 {
 #ifdef CONFIG_SPL_BUILD
 	clock_init_safe();
 #endif
 	clock_init_uart();
+	clock_init_sec();
 
 	return 0;
 }
diff --git a/arch/arm/cpu/armv7/sunxi/clock_sun6i.c b/arch/arm/cpu/armv7/sunxi/clock_sun6i.c
index 1da5455c9a..700b605ab3 100644
--- a/arch/arm/cpu/armv7/sunxi/clock_sun6i.c
+++ b/arch/arm/cpu/armv7/sunxi/clock_sun6i.c
@@ -45,6 +45,19 @@ void clock_init_safe(void)
 }
 #endif
 
+void clock_init_sec(void)
+{
+#ifdef CONFIG_MACH_SUN8I_H3
+	struct sunxi_ccm_reg * const ccm =
+		(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+
+	setbits_le32(&ccm->ccu_sec_switch,
+		     CCM_SEC_SWITCH_MBUS_NONSEC |
+		     CCM_SEC_SWITCH_BUS_NONSEC |
+		     CCM_SEC_SWITCH_PLL_NONSEC);
+#endif
+}
+
 void clock_init_uart(void)
 {
 #if CONFIG_CONS_INDEX < 5
diff --git a/arch/arm/cpu/armv7/sunxi/dram_sun8i_a83t.c b/arch/arm/cpu/armv7/sunxi/dram_sun8i_a83t.c
index d757e403dc..7c46acdbf2 100644
--- a/arch/arm/cpu/armv7/sunxi/dram_sun8i_a83t.c
+++ b/arch/arm/cpu/armv7/sunxi/dram_sun8i_a83t.c
@@ -25,6 +25,7 @@ struct dram_para {
 	u8 rank;
 	u8 rows;
 	u8 bus_width;
+	u8 dram_type;
 	u16 page_size;
 };
 
@@ -34,7 +35,7 @@ static void mctl_set_cr(struct dram_para *para)
 			(struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
 
 	writel(MCTL_CR_CS1_CONTROL(para->cs1) | MCTL_CR_UNKNOWN |
-		MCTL_CR_CHANNEL(1) | MCTL_CR_DDR3 |
+		MCTL_CR_CHANNEL(1) | MCTL_CR_DRAM_TYPE(para->dram_type) |
 		(para->seq ? MCTL_CR_SEQUENCE : 0) |
 		((para->bus_width == 16) ? MCTL_CR_BUSW16 : MCTL_CR_BUSW8) |
 		MCTL_CR_PAGE_SIZE(para->page_size) | MCTL_CR_ROW(para->rows) |
@@ -86,6 +87,7 @@ static void auto_set_timing_para(struct dram_para *para)
 {
 	struct sunxi_mctl_ctl_reg * const mctl_ctl =
 		(struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
+
 	u32 reg_val;
 
 	u8 tccd		= 2;
@@ -129,10 +131,42 @@ static void auto_set_timing_para(struct dram_para *para)
 	/* Set work mode register */
 	mctl_set_cr(para);
 	/* Set mode register */
-	writel(MCTL_MR0, &mctl_ctl->mr0);
-	writel(MCTL_MR1, &mctl_ctl->mr1);
-	writel(MCTL_MR2, &mctl_ctl->mr2);
-	writel(MCTL_MR3, &mctl_ctl->mr3);
+	if (para->dram_type == DRAM_TYPE_DDR3) {
+		writel(MCTL_MR0, &mctl_ctl->mr0);
+		writel(MCTL_MR1, &mctl_ctl->mr1);
+		writel(MCTL_MR2, &mctl_ctl->mr2);
+		writel(MCTL_MR3, &mctl_ctl->mr3);
+	} else if (para->dram_type == DRAM_TYPE_LPDDR3) {
+		writel(MCTL_LPDDR3_MR0, &mctl_ctl->mr0);
+		writel(MCTL_LPDDR3_MR1, &mctl_ctl->mr1);
+		writel(MCTL_LPDDR3_MR2, &mctl_ctl->mr2);
+		writel(MCTL_LPDDR3_MR3, &mctl_ctl->mr3);
+
+		/* timing parameters for LPDDR3 */
+		tfaw = max(ns_to_t(50), 4);
+		trrd = max(ns_to_t(10), 2);
+		trcd = max(ns_to_t(24), 2);
+		trc = ns_to_t(70);
+		txp = max(ns_to_t(8), 2);
+		twtr = max(ns_to_t(8), 2);
+		trtp = max(ns_to_t(8), 2);
+		trp = max(ns_to_t(27), 2);
+		tras = ns_to_t(42);
+		trefi = ns_to_t(3900) / 32;
+		trfc = ns_to_t(210);
+		tmrw		= 5;
+		tmrd		= 5;
+		tckesr		= 5;
+		tcwl		= 3;	/* CWL 8 */
+		t_rdata_en	= 5;
+		tdinit0	= (200 * CONFIG_DRAM_CLK) + 1;		/* 200us */
+		tdinit1	= (100 * CONFIG_DRAM_CLK) / 1000 + 1;	/* 100ns */
+		tdinit2	= (11 * CONFIG_DRAM_CLK) + 1;	/* 200us */
+		tdinit3	= (1 * CONFIG_DRAM_CLK) + 1;	/* 1us */
+		twtp	= tcwl + 4 + twr + 1;	/* CWL + BL/2 + tWR */
+		twr2rd	= tcwl + 4 + 1 + twtr;	/* WL + BL / 2 + tWTR */
+		trd2wr	= tcl + 4 + 5 - tcwl + 1; /* RL + BL / 2 + 2 - WL */
+	}
 	/* Set dram timing */
 	reg_val = (twtp << 24) | (tfaw << 16) | (trasmax << 8) | (tras << 0);
 	writel(reg_val, &mctl_ctl->dramtmg0);
@@ -287,6 +321,9 @@ static int mctl_channel_init(struct dram_para *para)
 	clrbits_le32(&mctl_ctl->pgcr2, (0x3 << 6));
 	clrbits_le32(&mctl_ctl->dqsgmr, (0x1 << 8) | (0x7));
 
+	if (para->dram_type == DRAM_TYPE_LPDDR3)
+		clrsetbits_le32(&mctl_ctl->dxccr, (0x1 << 27) | (0x3<<6) ,
+				0x1 << 31);
 	if (readl(&mctl_com->cr) & 0x1)
 		writel(0x00000303, &mctl_ctl->odtmap);
 	else
@@ -297,7 +334,11 @@ static int mctl_channel_init(struct dram_para *para)
 	clrsetbits_le32(ZQnPR(0), 0x000000ff, CONFIG_DRAM_ZQ & 0xff);
 	clrsetbits_le32(ZQnPR(1), 0x000000ff, (CONFIG_DRAM_ZQ >> 8) & 0xff);
 	/* CA calibration */
-	mctl_set_pir(0x0201f3 | 0x1<<10);
+
+	if (para->dram_type == DRAM_TYPE_DDR3)
+		mctl_set_pir(0x0201f3 | 0x1<<10);
+	else
+		mctl_set_pir(0x020173 | 0x1<<10);
 
 	/* DQS gate training */
 	if (mctl_train_dram(para) != 0) {
@@ -357,6 +398,7 @@ static void mctl_sys_init(struct dram_para *para)
 	clrbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MCTL);
 	clrbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_MCTL);
 	clrbits_le32(&ccm->pll5_cfg, CCM_PLL5_CTRL_EN);
+	udelay(1000);
 	clrbits_le32(&ccm->dram_clk_cfg, 0x01<<31);
 
 	clock_set_pll5(CONFIG_DRAM_CLK * 1000000 * DRAM_CLK_MUL);
@@ -366,16 +408,15 @@ static void mctl_sys_init(struct dram_para *para)
 			CCM_DRAMCLK_CFG_RST | CCM_DRAMCLK_CFG_UPD);
 	mctl_await_completion(&ccm->dram_clk_cfg, CCM_DRAMCLK_CFG_UPD, 0);
 
-	setbits_le32(&ccm->ahb_reset0_cfg, 1 << 14);
-	setbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MCTL);
-	setbits_le32(&ccm->mbus_reset, CCM_MBUS_RESET_RESET);
-	setbits_le32(&ccm->mbus_clk_cfg, MBUS_CLK_GATE);
-
 	setbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_MCTL);
 	setbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MCTL);
 	setbits_le32(&ccm->mbus_reset, CCM_MBUS_RESET_RESET);
 	setbits_le32(&ccm->mbus_clk_cfg, MBUS_CLK_GATE);
 
+	para->rank = 2;
+	para->bus_width = 16;
+	mctl_set_cr(para);
+
 	/* Set dram master access priority */
 	writel(0x0000e00f, &mctl_ctl->clken);	/* normal */
 
@@ -398,6 +439,13 @@ unsigned long sunxi_dram_init(void)
 		.page_size = 2048,
 	};
 
+#if defined(CONFIG_MACH_SUN8I_A83T)
+#if (CONFIG_DRAM_TYPE == 3) || (CONFIG_DRAM_TYPE == 7)
+	para.dram_type = CONFIG_DRAM_TYPE;
+#else
+#error Unsupported DRAM type, Please set DRAM type (3:DDR3, 7:LPDDR3)
+#endif
+#endif
 	setbits_le32(SUNXI_PRCM_BASE + 0x1e0, 0x1 << 8);
 
 	writel(0, (SUNXI_PRCM_BASE + 0x1e8));
diff --git a/arch/arm/cpu/armv7/sunxi/psci_sun6i.S b/arch/arm/cpu/armv7/sunxi/psci_sun6i.S
index 4ff46e4fc0..90b5bfd359 100644
--- a/arch/arm/cpu/armv7/sunxi/psci_sun6i.S
+++ b/arch/arm/cpu/armv7/sunxi/psci_sun6i.S
@@ -106,7 +106,7 @@ psci_fiq_enter:
 	str	r10, [r8, #0x100]
 	timer_wait r10, ONE_MS
 
-#ifdef CONFIG_MACH_SUN6I
+#if defined(CONFIG_MACH_SUN6I) || defined(CONFIG_MACH_SUN8I_H3)
 	@ Activate power clamp
 	lsl	r12, r9, #2		@ x4
 	add	r12, r12, r8
@@ -170,7 +170,7 @@ psci_cpu_on:
 	movw	r0, #(SUNXI_PRCM_BASE & 0xffff)
 	movt	r0, #(SUNXI_PRCM_BASE >> 16)
 
-#ifdef CONFIG_MACH_SUN6I
+#if defined(CONFIG_MACH_SUN6I) || defined(CONFIG_MACH_SUN8I_H3)
 	@ Release power clamp
 	lsl	r5, r1, #2	@ 1 register per CPU
 	add	r5, r5, r0	@ PRCM
diff --git a/arch/arm/cpu/armv7/sunxi/tzpc.c b/arch/arm/cpu/armv7/sunxi/tzpc.c
index 5c9c69b20b..6c8a0fd9a2 100644
--- a/arch/arm/cpu/armv7/sunxi/tzpc.c
+++ b/arch/arm/cpu/armv7/sunxi/tzpc.c
@@ -13,6 +13,15 @@ void tzpc_init(void)
 {
 	struct sunxi_tzpc *tzpc = (struct sunxi_tzpc *)SUNXI_TZPC_BASE;
 
+#ifdef CONFIG_MACH_SUN6I
 	/* Enable non-secure access to the RTC */
-	writel(SUNXI_TZPC_DECPORT0_RTC, &tzpc->decport0_set);
+	writel(SUN6I_TZPC_DECPORT0_RTC, &tzpc->decport0_set);
+#endif
+
+#ifdef CONFIG_MACH_SUN8I_H3
+	/* Enable non-secure access to all peripherals */
+	writel(SUN8I_H3_TZPC_DECPORT0_ALL, &tzpc->decport0_set);
+	writel(SUN8I_H3_TZPC_DECPORT1_ALL, &tzpc->decport1_set);
+	writel(SUN8I_H3_TZPC_DECPORT2_ALL, &tzpc->decport2_set);
+#endif
 }