diff options
| author | Wenbin song <wenbin.song@nxp.com> | 2017-12-04 12:18:28 +0800 |
|---|---|---|
| committer | York Sun <york.sun@nxp.com> | 2017-12-13 13:40:29 -0800 |
| commit | a8f33034f2ed029dd04aae4cfdf11bf1f13a03a2 (patch) | |
| tree | a28d800134e70495cd7988350956da12e24e5ff4 /arch/arm/cpu | |
| parent | 4c616a13de3e1cd526009e39a56674ba60e9c769 (diff) | |
armv8: ls1043a/ls2080a: check SoC by device ID
Check LS1043A/LS2080a by device ID without using personality ID to
determine revision number. This check applies to all various
personalities of the same SoC family.
Signed-off-by: Wenbin Song <wenbin.song@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Diffstat (limited to 'arch/arm/cpu')
| -rw-r--r-- | arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 8 | ||||
| -rw-r--r-- | arch/arm/cpu/armv8/fsl-layerscape/fdt.c | 4 | ||||
| -rw-r--r-- | arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S | 9 |
3 files changed, 10 insertions, 11 deletions
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index d08262971e..00d2564c79 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -538,8 +538,8 @@ int arch_early_init_r(void) * erratum A009635 is valid only for LS2080A SoC and * its personalitiesi */ - svr_dev_id = get_svr() >> 16; - if (svr_dev_id == SVR_DEV_LS2080A) + svr_dev_id = get_svr(); + if (IS_SVR_DEV(svr_dev_id, SVR_DEV(SVR_LS2080A))) erratum_a009635(); #endif #if defined(CONFIG_SYS_FSL_ERRATUM_A009942) && defined(CONFIG_SYS_FSL_DDR) @@ -604,8 +604,8 @@ int timer_init(void) * For LS2080A SoC and its personalities, timer controller * offset is different */ - svr_dev_id = get_svr() >> 16; - if (svr_dev_id == SVR_DEV_LS2080A) + svr_dev_id = get_svr(); + if (IS_SVR_DEV(svr_dev_id, SVR_DEV(SVR_LS2080A))) cntcr = (u32 *)SYS_FSL_LS2080A_LS2085A_TIMER_ADDR; #endif diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c index cae59da803..d1a7d0de9c 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c @@ -145,7 +145,7 @@ static void fdt_fixup_gic(void *blob) val = gur_in32(&gur->svr); - if (SVR_SOC_VER(val) != SVR_LS1043A) { + if (!IS_SVR_DEV(val, SVR_DEV(SVR_LS1043A))) { align_64k = 1; } else if (SVR_REV(val) != REV1_0) { val = scfg_in32(&scfg->gic_align) & (0x01 << GIC_ADDR_BIT); @@ -327,7 +327,7 @@ static void fdt_fixup_msi(void *blob) rev = gur_in32(&gur->svr); - if (SVR_SOC_VER(rev) != SVR_LS1043A) + if (!IS_SVR_DEV(rev, SVR_DEV(SVR_LS1043A))) return; rev = SVR_REV(rev); diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S index fa93096c68..c089ceef32 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S +++ b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S @@ -37,9 +37,8 @@ ENTRY(get_gic_offset) ldr x2, =DCFG_CCSR_SVR ldr w2, [x2] rev w2, w2 - mov w3, w2 - ands w3, w3, #SVR_WO_E << 8 - mov w4, #SVR_LS1043A << 8 + lsr w3, w2, #16 + ldr w4, =SVR_DEV(SVR_LS1043A) cmp w3, w4 b.ne 1f ands w2, w2, #0xff @@ -92,7 +91,7 @@ ENTRY(lowlevel_init) */ bl get_svr lsr w0, w0, #16 - ldr w1, =SVR_DEV_LS2080A + ldr w1, =SVR_DEV(SVR_LS2080A) cmp w0, w1 b.eq 1f @@ -224,7 +223,7 @@ ENTRY(lowlevel_init) */ bl get_svr lsr w0, w0, #16 - ldr w1, =SVR_DEV_LS2080A + ldr w1, =SVR_DEV(SVR_LS2080A) cmp w0, w1 b.eq 1f |