diff options
| author | Alison Wang <b18965@freescale.com> | 2016-04-22 10:37:25 +0800 |
|---|---|---|
| committer | York Sun <york.sun@nxp.com> | 2016-05-18 08:51:44 -0700 |
| commit | acb8f5e914814ac6c697edb86701958da251a223 (patch) | |
| tree | 4bf28ce36b7195333b3a51741105b63329e6ee64 /arch/arm/cpu | |
| parent | 7ad9cc969b00cd5e238f4a194f0e974d74706b8e (diff) | |
armv8: fsl-layerscape: Remove unnecessary flushing dcache
As the issue about the stack will get corrupted when switching between
the early and final mmu tables is fixed by commit 70e21b064, the
workaround to flush dcache is unnecessary and should be removed.
Signed-off-by: Alison Wang <alison.wang@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Diffstat (limited to 'arch/arm/cpu')
| -rw-r--r-- | arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 3 |
1 files changed, 0 insertions, 3 deletions
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index d93990036b..9a5a6b53f7 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -396,9 +396,6 @@ static inline void final_mmu_setup(void) flush_dcache_range((ulong)level0_table, (ulong)level0_table + gd->arch.tlb_size); -#ifdef CONFIG_SYS_DPAA_FMAN - flush_dcache_all(); -#endif /* point TTBR to the new table */ set_ttbr_tcr_mair(el, (u64)level0_table, LAYERSCAPE_TCR_FINAL, MEMORY_ATTRIBUTES); |