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authorLaurentiu Tudor <laurentiu.tudor@nxp.com>2019-07-30 17:29:57 +0300
committerPrabhakar Kushwaha <prabhakar.kushwaha@nxp.com>2019-08-22 09:07:36 +0530
commitaef654a2ed386d8bd53053383f6bf15ba016a79c (patch)
tree7dcfb1c5f8418120183dba9542a29eb74cb5f9e8 /arch/arm/cpu
parent08f9bc9f4332e13a4ba4705d84d62e41a45b3fbe (diff)
armv8: fsl-layerscape: make icid setup endianness aware
The current implementation assumes that the registers holding the ICIDs are universally big endian. That's no longer the case on newer platforms so update the code to take into account the endianness of each register. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Horia Geantă <horia.geanta@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Diffstat (limited to 'arch/arm/cpu')
-rw-r--r--arch/arm/cpu/armv8/fsl-layerscape/icid.c5
1 files changed, 4 insertions, 1 deletions
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/icid.c b/arch/arm/cpu/armv8/fsl-layerscape/icid.c
index b1a950e7f9..82c5a8b123 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/icid.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/icid.c
@@ -17,7 +17,10 @@ static void set_icid(struct icid_id_table *tbl, int size)
int i;
for (i = 0; i < size; i++)
- out_be32((u32 *)(tbl[i].reg_addr), tbl[i].reg);
+ if (tbl[i].le)
+ out_le32((u32 *)(tbl[i].reg_addr), tbl[i].reg);
+ else
+ out_be32((u32 *)(tbl[i].reg_addr), tbl[i].reg);
}
#ifdef CONFIG_SYS_DPAA_FMAN