diff options
| author | Ashish Kumar <Ashish.Kumar@nxp.com> | 2017-08-18 10:54:36 +0530 |
|---|---|---|
| committer | York Sun <york.sun@nxp.com> | 2017-09-11 07:55:36 -0700 |
| commit | c055cee1951a01a3306f54f20bcfb85adf28721a (patch) | |
| tree | b59727a8075cfc4b7375f3686b38581f9de9d466 /arch/arm/cpu | |
| parent | c8bc3c0c9ff7ce649b2af1416919b50ecf504874 (diff) | |
armv8: fsl-lsch3: Make CCN-504 related code conditional
LS2080 family has CCN-504 cache coherent interconnet. Other SoCs
in LSCH3 family may have differnt interconnect.
Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
[YS: revised commit message]
Reviewed-by: York Sun <york.sun@nxp.com>
Diffstat (limited to 'arch/arm/cpu')
| -rw-r--r-- | arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 4 | ||||
| -rw-r--r-- | arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S | 8 |
2 files changed, 9 insertions, 3 deletions
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index cdadd38a12..d72f8f84d4 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -61,6 +61,7 @@ config ARCH_LS2080A select SYS_FSL_DDR select SYS_FSL_DDR_LE select SYS_FSL_DDR_VER_50 + select SYS_FSL_HAS_CCN504 select SYS_FSL_HAS_DP_DDR select SYS_FSL_HAS_SEC select SYS_FSL_HAS_DDR4 @@ -269,6 +270,9 @@ config SYS_FSL_IFC_BANK_COUNT config SYS_FSL_HAS_CCI400 bool +config SYS_FSL_HAS_CCN504 + bool + config SYS_FSL_HAS_DP_DDR bool diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S index 3136e3f3a2..5ff01a0e1b 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S +++ b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S @@ -76,7 +76,7 @@ ENTRY(lowlevel_init) switch_el x1, 1f, 100f, 100f /* skip if not in EL3 */ 1: -#ifdef CONFIG_FSL_LSCH3 +#if defined (CONFIG_SYS_FSL_HAS_CCN504) /* Set Wuo bit for RN-I 20 */ #ifdef CONFIG_ARCH_LS2080A @@ -171,7 +171,7 @@ ENTRY(lowlevel_init) ldr x0, =CCI_S2_QOS_CONTROL_BASE(20) ldr x1, =0x00FF000C bl ccn504_set_qos -#endif +#endif /* CONFIG_SYS_FSL_HAS_CCN504 */ #ifdef SMMU_BASE /* Set the SMMU page size in the sACR register */ @@ -338,7 +338,9 @@ get_svr: ldr x1, =FSL_LSCH3_SVR ldr w0, [x1] ret +#endif +#ifdef CONFIG_SYS_FSL_HAS_CCN504 hnf_pstate_poll: /* x0 has the desired status, return 0 for success, 1 for timeout * clobber x1, x2, x3, x4, x6, x7 @@ -420,7 +422,7 @@ ENTRY(__asm_flush_l3_dcache) mov lr, x29 ret ENDPROC(__asm_flush_l3_dcache) -#endif +#endif /* CONFIG_SYS_FSL_HAS_CCN504 */ #ifdef CONFIG_MP /* Keep literals not used by the secondary boot code outside it */ |