diff options
| author | Michal Simek <michal.simek@xilinx.com> | 2013-08-28 08:26:41 +0200 |
|---|---|---|
| committer | Michal Simek <michal.simek@xilinx.com> | 2013-11-06 09:23:58 +0100 |
| commit | c1824ea268b1a565fd6956d79a91e4460d88a88b (patch) | |
| tree | 813124c10624f418f57b239ed7052415fcda3fc8 /arch/arm/cpu | |
| parent | c0e5dd88c438a41bf180dde0c2dc4c67dcd8058d (diff) | |
arm: zynq: Do not remap OCM to high address
In case where ps-ddr is not used, do not remap
OCM to high address and keep it from 0x0.
Linux SMP requires to have memory at 0x0.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Diffstat (limited to 'arch/arm/cpu')
| -rw-r--r-- | arch/arm/cpu/armv7/zynq/cpu.c | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/arch/arm/cpu/armv7/zynq/cpu.c b/arch/arm/cpu/armv7/zynq/cpu.c index 2bb38438ae..0ca5d8a97a 100644 --- a/arch/arm/cpu/armv7/zynq/cpu.c +++ b/arch/arm/cpu/armv7/zynq/cpu.c @@ -16,13 +16,15 @@ void lowlevel_init(void) int arch_cpu_init(void) { zynq_slcr_unlock(); - /* remap DDR to zero, FILTERSTART */ - writel(0, &scu_base->filter_start); /* Device config APB, unlock the PCAP */ writel(0x757BDF0D, &devcfg_base->unlock); writel(0xFFFFFFFF, &devcfg_base->rom_shadow); +#if (CONFIG_SYS_SDRAM_BASE == 0) + /* remap DDR to zero, FILTERSTART */ + writel(0, &scu_base->filter_start); + /* OCM_CFG, Mask out the ROM, map ram into upper addresses */ writel(0x1F, &slcr_base->ocm_cfg); /* FPGA_RST_CTRL, clear resets on AXI fabric ports */ @@ -33,6 +35,7 @@ int arch_cpu_init(void) writel(0x0, &slcr_base->ddr_urgent_sel); /* Urgent write, ports S2/S3 */ writel(0xC, &slcr_base->ddr_urgent); +#endif zynq_slcr_lock(); |