diff options
| author | York Sun <york.sun@nxp.com> | 2016-12-28 08:43:40 -0800 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2017-01-04 19:40:41 -0500 |
| commit | d26e34c4c4b6473fdbd412a3b2dc33a94b08e8ff (patch) | |
| tree | 22eaf9594d9a0b0dbbe31a489a7a80f751939b1a /arch/arm/cpu | |
| parent | a10550385169e456950add6f3e2a4774d6aea67c (diff) | |
fsl_ddr: Move DDR config options to driver Kconfig
Create driver/ddr/fsl/Kconfig and move existing options. Clean up
existing macros.
Signed-off-by: York Sun <york.sun@nxp.com>
[trini: Migrate sbc8641d, xpedite537x and MPC8536DS, run a moveconfig.py -s]
Signed-off-by: Tom Rini <trini@konsulko.com>
Diffstat (limited to 'arch/arm/cpu')
| -rw-r--r-- | arch/arm/cpu/armv7/ls102xa/Kconfig | 47 | ||||
| -rw-r--r-- | arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 57 |
2 files changed, 11 insertions, 93 deletions
diff --git a/arch/arm/cpu/armv7/ls102xa/Kconfig b/arch/arm/cpu/armv7/ls102xa/Kconfig index d154f7b0f6..eca1d06ca5 100644 --- a/arch/arm/cpu/armv7/ls102xa/Kconfig +++ b/arch/arm/cpu/armv7/ls102xa/Kconfig @@ -3,8 +3,10 @@ config ARCH_LS1021A select SYS_FSL_ERRATUM_A010315 select SYS_FSL_SRDS_1 select SYS_HAS_SERDES - select SYS_FSL_DDR_BE - select SYS_FSL_DDR_VER_50 + select SYS_FSL_DDR_BE if SYS_FSL_DDR + select SYS_FSL_DDR_VER_50 if SYS_FSL_DDR + select SYS_FSL_HAS_DDR3 if SYS_FSL_DDR + select SYS_FSL_HAS_DDR4 if SYS_FSL_DDR select SYS_FSL_HAS_SEC select SYS_FSL_SEC_COMPAT_5 select SYS_FSL_SEC_LE @@ -49,47 +51,6 @@ config SYS_FSL_SRDS_2 config SYS_HAS_SERDES bool -config SYS_FSL_DDR - bool "Freescale DDR driver" - help - Select Freescale General DDR driver, shared between most Freescale - PowerPC- based SoCs (such as mpc83xx, mpc85xx, mpc86xx) and ARM- - based Layerscape SoCs (such as ls2080a). - -config SYS_FSL_DDR_BE - bool - default y - help - Access DDR registers in big-endian. - -config SYS_FSL_DDR_VER - int - default 50 if SYS_FSL_DDR_VER_50 - -config SYS_FSL_DDR_VER_50 - bool - -config SYS_FSL_DDRC_ARM_GEN3 - bool - -config SYS_FSL_DDRC_GEN4 - bool - -config SYS_FSL_DDR3 - bool "Freescale DDR3 controller" - depends on !SYS_FSL_DDR4 - select SYS_FSL_DDR - select SYS_FSL_DDRC_ARM_GEN3 - help - Enable Freescale DDR3 controller on ARM-based SoCs. - -config SYS_FSL_DDR4 - bool "Freescale DDR4 controller" - select SYS_FSL_DDR - select SYS_FSL_DDRC_GEN4 - help - Enable Freescale DDR4 controller. - config SYS_FSL_IFC_BANK_COUNT int "Maximum banks of Integrated flash controller" depends on ARCH_LS1021A diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index a1f781edb7..bee7d1537c 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -8,28 +8,33 @@ config ARCH_LS1012A config ARCH_LS1043A bool select FSL_LSCH2 + select SYS_FSL_DDR select SYS_FSL_DDR_BE select SYS_FSL_DDR_VER_50 select SYS_FSL_ERRATUM_A010315 select SYS_FSL_ERRATUM_A010539 + select SYS_FSL_HAS_DDR3 + select SYS_FSL_HAS_DDR4 config ARCH_LS1046A bool select FSL_LSCH2 + select SYS_FSL_DDR select SYS_FSL_DDR_BE - select SYS_FSL_DDR4 select SYS_FSL_DDR_VER_50 select SYS_FSL_ERRATUM_A010539 + select SYS_FSL_HAS_DDR4 select SYS_FSL_SRDS_2 config ARCH_LS2080A bool select FSL_LSCH3 - select SYS_FSL_DDR4 + select SYS_FSL_DDR select SYS_FSL_DDR_LE select SYS_FSL_DDR_VER_50 select SYS_FSL_HAS_DP_DDR select SYS_FSL_HAS_SEC + select SYS_FSL_HAS_DDR4 select SYS_FSL_SEC_COMPAT_5 select SYS_FSL_SEC_LE select SYS_FSL_SRDS_2 @@ -71,9 +76,6 @@ config FSL_PPA_ARMV8_PSCI implemented under the common ARMv8 PSCI framework. endmenu -config SYS_FSL_MMDC - bool - config SYS_FSL_ERRATUM_A010315 bool "Workaround for PCIe erratum A010315" @@ -129,49 +131,4 @@ config SYS_FSL_SRDS_2 config SYS_HAS_SERDES bool -config SYS_FSL_DDR - bool "Freescale DDR driver" - help - Select Freescale General DDR driver, shared between most Freescale - PowerPC- based SoCs (such as mpc83xx, mpc85xx, mpc86xx) and ARM- - based Layerscape SoCs (such as ls2080a). - -config SYS_FSL_DDR_BE - bool - help - Access DDR registers in big-endian. - -config SYS_FSL_DDR_LE - bool - help - Access DDR registers in little-endian. - -config SYS_FSL_DDR_VER - int - default 50 if SYS_FSL_DDR_VER_50 - -config SYS_FSL_DDR_VER_50 - bool - -config SYS_FSL_DDRC_ARM_GEN3 - bool - -config SYS_FSL_DDRC_GEN4 - bool - -config SYS_FSL_DDR3 - bool "Freescale DDR3 controller" - depends on !SYS_FSL_DDR4 - select SYS_FSL_DDR - select SYS_FSL_DDRC_ARM_GEN3 - help - Enable Freescale DDR3 controller on ARM-based SoCs. - -config SYS_FSL_DDR4 - bool "Freescale DDR4 controller" - select SYS_FSL_DDR - select SYS_FSL_DDRC_GEN4 - help - Enable Freescale DDR4 controller. - endmenu |