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authorFaiz Abbas <faiz_abbas@ti.com>2019-06-20 15:07:19 +0530
committerTom Rini <trini@konsulko.com>2019-07-26 22:24:10 -0400
commit461918d7df7bd356717a5f81ca58f1c8ca7ae1fb (patch)
tree95b32f7b35940779dc322bbce3fcc7516d40a9aa /arch/arm/dts/am571x-idk.dts
parent697a689d76ef463623371779c78a97c13477c955 (diff)
ARM: dts: dra7-mmc-iodelay: Add a new pinctrl group for clk line without pullup
During a short period when the bus voltage is switched from 3.3v to 1.8v, (to enumerate UHS mode), the mmc module is disabled and the mmc IO lines are kept in a state according to the programmed pad mux pull type. According to 4.2.4.2 Timing to Switch Signal Voltage in "SD Specifications Part 1 Physical Layer Specification Version 5.00 February 22, 2016", the host should hold CLK low for at least 5ms. In order to keep the card line low during voltage switch, the pad mux of mmc1_clk line should be configured to pull down. Add a new pinctrl group for clock line without pullup to be used in boards where mmc1_clk line is not connected to an external pullup. Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
Diffstat (limited to 'arch/arm/dts/am571x-idk.dts')
-rw-r--r--arch/arm/dts/am571x-idk.dts3
1 files changed, 2 insertions, 1 deletions
diff --git a/arch/arm/dts/am571x-idk.dts b/arch/arm/dts/am571x-idk.dts
index debf946440..eb5fda81f5 100644
--- a/arch/arm/dts/am571x-idk.dts
+++ b/arch/arm/dts/am571x-idk.dts
@@ -11,6 +11,7 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include "am57xx-idk-common.dtsi"
+#include "dra7-mmc-iodelay.dtsi"
#include "dra72x-mmc-iodelay.dtsi"
/ {
@@ -102,7 +103,7 @@
&mmc1 {
pinctrl-names = "default", "hs", "sdr12", "sdr25", "sdr50", "ddr50", "sdr104";
- pinctrl-0 = <&mmc1_pins_default>;
+ pinctrl-0 = <&mmc1_pins_default_no_clk_pu>;
pinctrl-1 = <&mmc1_pins_hs>;
pinctrl-2 = <&mmc1_pins_sdr12>;
pinctrl-3 = <&mmc1_pins_sdr25>;