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authorJaehoon Chung <jh80.chung@samsung.com>2017-11-28 16:20:39 +0900
committerMinkyu Kang <mk7.kang@samsung.com>2017-12-05 10:18:39 +0900
commitd8b385b708ba5405a4921835f7104c598850785c (patch)
tree4ba7041262b2a6240ae10cb2dca2d9f1c5920670 /arch/arm/dts/exynos4210.dtsi
parent9da7fb4a39149c3061cb148bfbaa76b4b52b9008 (diff)
arm: dts: exynos4: fix the device-tree compile warning
After updating dtc-1.4.5 version, there are too many warning. This patch is to fix about exynos4 series. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Diffstat (limited to 'arch/arm/dts/exynos4210.dtsi')
-rw-r--r--arch/arm/dts/exynos4210.dtsi20
1 files changed, 12 insertions, 8 deletions
diff --git a/arch/arm/dts/exynos4210.dtsi b/arch/arm/dts/exynos4210.dtsi
index 634a5c1dd2..b04a86b827 100644
--- a/arch/arm/dts/exynos4210.dtsi
+++ b/arch/arm/dts/exynos4210.dtsi
@@ -41,14 +41,6 @@
cpu-offset = <0x8000>;
};
- combiner: interrupt-controller@10440000 {
- samsung,combiner-nr = <16>;
- interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
- <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>,
- <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>,
- <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>;
- };
-
mct@10050000 {
compatible = "samsung,exynos4210-mct";
reg = <0x10050000 0x800>;
@@ -85,12 +77,14 @@
pinctrl_0: pinctrl@11400000 {
compatible = "samsung,exynos4210-pinctrl";
reg = <0x11400000 0x1000>;
+ interrupt-parent = <&gic>;
interrupts = <0 47 0>;
};
pinctrl_1: pinctrl@11000000 {
compatible = "samsung,exynos4210-pinctrl";
reg = <0x11000000 0x1000>;
+ interrupt-parent = <&gic>;
interrupts = <0 46 0>;
wakup_eint: wakeup-interrupt-controller {
@@ -118,6 +112,7 @@
g2d@12800000 {
compatible = "samsung,s5pv210-g2d";
reg = <0x12800000 0x1000>;
+ interrupt-parent = <&gic>;
interrupts = <0 89 0>;
clocks = <&clock 177>, <&clock 277>;
clock-names = "sclk_fimg2d", "fimg2d";
@@ -154,3 +149,12 @@
};
};
};
+
+&combiner {
+ samsung,combiner-nr = <16>;
+ interrupt-parent = <&gic>;
+ interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
+ <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>,
+ <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>,
+ <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>;
+};