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authorTom Rini <trini@konsulko.com>2019-06-11 13:41:24 -0400
committerTom Rini <trini@konsulko.com>2019-06-11 13:41:24 -0400
commit529faf80c339b78bd361b59735664f2605322b8e (patch)
tree2186ebe6f8f713d0dd497eb9d20c1a30e64105bb /arch/arm/dts/fsl-imx8qxp-colibri-u-boot.dtsi
parent68b90e57bc034e237923b02acb633dc4e91d44cb (diff)
parent23612534fe0fe426716ee9cb5cfeb74a456cb891 (diff)
Merge tag 'u-boot-imx-20190612' of git://git.denx.de/u-boot-imx
u-boot-imx-20190612 -------------------- - Board fixes: - imx6logic - wandboard - mx6sabre boots again - imx8qm_mek - pico-* boards - Toradex apalis / colibri - engicam imx6 (environment) - KP MX53 - opos6ul - Switch to DM: - vining2000 - dh MX6 - Toradex colibri i.MX7 - Novena - Security : fix CSF size for HAB - Other: - imx: fix building for i.mx8 without spl - pcie and switch to DM mx6sabreauto: Enable SPL SDP support
Diffstat (limited to 'arch/arm/dts/fsl-imx8qxp-colibri-u-boot.dtsi')
-rw-r--r--arch/arm/dts/fsl-imx8qxp-colibri-u-boot.dtsi117
1 files changed, 117 insertions, 0 deletions
diff --git a/arch/arm/dts/fsl-imx8qxp-colibri-u-boot.dtsi b/arch/arm/dts/fsl-imx8qxp-colibri-u-boot.dtsi
new file mode 100644
index 0000000000..5b061f94ba
--- /dev/null
+++ b/arch/arm/dts/fsl-imx8qxp-colibri-u-boot.dtsi
@@ -0,0 +1,117 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * Copyright 2019 Toradex AG
+ */
+
+&{/imx8qx-pm} {
+
+ u-boot,dm-spl;
+};
+
+&mu {
+ u-boot,dm-spl;
+};
+
+&clk {
+ u-boot,dm-spl;
+};
+
+&iomuxc {
+ u-boot,dm-spl;
+};
+
+&pd_lsio {
+ u-boot,dm-spl;
+};
+
+&pd_lsio_gpio0 {
+ u-boot,dm-spl;
+};
+
+&pd_lsio_gpio1 {
+ u-boot,dm-spl;
+};
+
+&pd_lsio_gpio2 {
+ u-boot,dm-spl;
+};
+
+&pd_lsio_gpio3 {
+ u-boot,dm-spl;
+};
+
+&pd_lsio_gpio4 {
+ u-boot,dm-spl;
+};
+
+&pd_lsio_gpio5 {
+ u-boot,dm-spl;
+};
+
+&pd_lsio_gpio6 {
+ u-boot,dm-spl;
+};
+
+&pd_lsio_gpio7 {
+ u-boot,dm-spl;
+};
+
+&pd_conn {
+ u-boot,dm-spl;
+};
+
+&pd_conn_sdch0 {
+ u-boot,dm-spl;
+};
+
+&pd_conn_sdch1 {
+ u-boot,dm-spl;
+};
+
+&pd_conn_sdch2 {
+ u-boot,dm-spl;
+};
+
+&gpio0 {
+ u-boot,dm-spl;
+};
+
+&gpio1 {
+ u-boot,dm-spl;
+};
+
+&gpio2 {
+ u-boot,dm-spl;
+};
+
+&gpio3 {
+ u-boot,dm-spl;
+};
+
+&gpio4 {
+ u-boot,dm-spl;
+};
+
+&gpio5 {
+ u-boot,dm-spl;
+};
+
+&gpio6 {
+ u-boot,dm-spl;
+};
+
+&gpio7 {
+ u-boot,dm-spl;
+};
+
+&lpuart3 {
+ u-boot,dm-spl;
+};
+
+&usdhc1 {
+ u-boot,dm-spl;
+};
+
+&usdhc2 {
+ u-boot,dm-spl;
+};