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authorAbhimanyu Saini <abhimanyu.saini@nxp.com>2016-06-14 13:18:31 +0530
committerYork Sun <york.sun@nxp.com>2016-06-28 12:08:54 -0700
commitdee01e426b39eac974364c0658fca431894987c3 (patch)
tree5c756e9740a9c8477e03421daf9dc172b76c932a /arch/arm/dts/fsl-ls1012a.dtsi
parent49cdce163519ad760ca7769be64dd2a6133a5c11 (diff)
armv8: dts: fsl: Remove cpu nodes from Layerscape DTSIs
Currently layescape SoCs are not using cpu nodes. So removing them in favour of compatibly with similar SoCs that have different cores like LS2080A and LS2088A. This has been tested on LS2080AQDS, LS1043ARDB, LS1012ARDB. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Signed-off-by: Abhimanyu Saini <abhimanyu.saini@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
Diffstat (limited to 'arch/arm/dts/fsl-ls1012a.dtsi')
-rw-r--r--arch/arm/dts/fsl-ls1012a.dtsi12
1 files changed, 0 insertions, 12 deletions
diff --git a/arch/arm/dts/fsl-ls1012a.dtsi b/arch/arm/dts/fsl-ls1012a.dtsi
index 546a87a0a5..024527e815 100644
--- a/arch/arm/dts/fsl-ls1012a.dtsi
+++ b/arch/arm/dts/fsl-ls1012a.dtsi
@@ -9,18 +9,6 @@
/ {
compatible = "fsl,ls1012a";
interrupt-parent = <&gic>;
- cpus {
- #address-cells = <2>;
- #size-cells = <0>;
-
- cpu0: cpu@0 {
- device_type = "cpu";
- compatible = "arm,cortex-a53";
- reg = <0x0 0x0>;
- clocks = <&clockgen 1 0>;
- };
-
- };
sysclk: sysclk {
compatible = "fixed-clock";