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| author | Alexey Brodkin <abrodkin@synopsys.com> | 2017-04-05 17:50:09 +0300 |
|---|---|---|
| committer | Alexey Brodkin <abrodkin@synopsys.com> | 2017-04-11 17:54:31 +0300 |
| commit | 40a808f173008729a0c631ab84693b6a2b0dcfc9 (patch) | |
| tree | fb155b0055b7e2fefd21aaec397ef251f48fdc71 /arch/arm/dts/fsl-ls1043a-qds-lpuart.dts | |
| parent | 9963890b8be1d208035945abc5ba9f77637b6542 (diff) | |
ARCv2: SLC: Make sure busy bit is set properly on SLC flushing
As reported in STAR 9001165532, an SLC control reg read (for checking
busy state) right after SLC invalidate command may incorrectly return
NOT busy causing software to NOT spin-wait while operation is underway.
(and for some reason this only happens if L1 cache is also disabled - as
required by IOC programming model)
Suggested workaround is to do an additional Control Reg read, which
ensures the 2nd read gets the right status.
Same fix made in Linux kernel:
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=c70c473396cbdec1168a6eff60e13029c0916854
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Diffstat (limited to 'arch/arm/dts/fsl-ls1043a-qds-lpuart.dts')
0 files changed, 0 insertions, 0 deletions