diff options
author | Madalin Bucur <madalin.bucur@oss.nxp.com> | 2020-04-23 16:25:15 +0300 |
---|---|---|
committer | Priyanka Jain <priyanka.jain@nxp.com> | 2020-04-29 11:10:54 +0530 |
commit | 8de6301dd8d8f02c134c8d6429cfdc775c82154d (patch) | |
tree | 8d0c27da6d5750c58bdb04abf6e78ffea4c6571b /arch/arm/dts/fsl-ls1046a-rdb.dts | |
parent | acbb98c06228bf4cbb3c32f3fcb291490796ead6 (diff) |
ARM: dts: add QorIQ DPAA 1 FMan v3 to LS1046ARDB
Introduce the QorIQ DPAA 1 Frame Manager nodes in the LS1046ARDB
device tree. The device tree fragments are copied over with little
modification from the Linux kernel source code.
Signed-off-by: Madalin Bucur <madalin.bucur@oss.nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Diffstat (limited to 'arch/arm/dts/fsl-ls1046a-rdb.dts')
-rw-r--r-- | arch/arm/dts/fsl-ls1046a-rdb.dts | 67 |
1 files changed, 67 insertions, 0 deletions
diff --git a/arch/arm/dts/fsl-ls1046a-rdb.dts b/arch/arm/dts/fsl-ls1046a-rdb.dts index 83e34ab02a..cac65a7afa 100644 --- a/arch/arm/dts/fsl-ls1046a-rdb.dts +++ b/arch/arm/dts/fsl-ls1046a-rdb.dts @@ -3,6 +3,7 @@ * Device Tree Include file for Freescale Layerscape-1046A family SoC. * * Copyright 2016, Freescale Semiconductor + * Copyright 2020 NXP * * Mingkai Hu <Mingkai.hu@freescale.com> */ @@ -51,3 +52,69 @@ &i2c3 { status = "okay"; }; + +#include "fsl-ls1046-post.dtsi" + +&fman0 { + ethernet@e4000 { + phy-handle = <&rgmii_phy1>; + phy-connection-type = "rgmii-id"; + status = "okay"; + }; + + ethernet@e6000 { + phy-handle = <&rgmii_phy2>; + phy-connection-type = "rgmii-id"; + status = "okay"; + }; + + ethernet@e8000 { + phy-handle = <&sgmii_phy1>; + phy-connection-type = "sgmii"; + status = "okay"; + }; + + ethernet@ea000 { + phy-handle = <&sgmii_phy2>; + phy-connection-type = "sgmii"; + status = "okay"; + }; + + ethernet@f0000 { /* 10GEC1 */ + phy-handle = <&aqr106_phy>; + phy-connection-type = "xgmii"; + status = "okay"; + }; + + ethernet@f2000 { /* 10GEC2 */ + fixed-link = <0 1 1000 0 0>; + phy-connection-type = "xgmii"; + status = "okay"; + }; + + mdio@fc000 { + rgmii_phy1: ethernet-phy@1 { + reg = <0x1>; + }; + + rgmii_phy2: ethernet-phy@2 { + reg = <0x2>; + }; + + sgmii_phy1: ethernet-phy@3 { + reg = <0x3>; + }; + + sgmii_phy2: ethernet-phy@4 { + reg = <0x4>; + }; + }; + + mdio@fd000 { + aqr106_phy: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c45"; + interrupts = <0 131 4>; + reg = <0x0>; + }; + }; +}; |