diff options
| author | Tom Rini <trini@konsulko.com> | 2020-09-25 12:55:06 -0400 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2020-09-25 12:55:06 -0400 |
| commit | 253388acd6d0d52205ed9a32282f990e055bb87d (patch) | |
| tree | a84e1d53a94b4ea3dbf1d1994ebf02606aa41503 /arch/arm/dts/fsl-lx2160a.dtsi | |
| parent | 1da91d9bcd6e5ef046c1df0d373d0df87b1e8a72 (diff) | |
| parent | 8ec619f8fd847eb80d75fa0a582e1fa3c74a21a7 (diff) | |
Merge https://gitlab.denx.de/u-boot/custodians/u-boot-fsl-qoriq
- Bug fixes related to PCIe, pfe, xfi, gpio, reset, vid, env, and usb on
layerscape products
Diffstat (limited to 'arch/arm/dts/fsl-lx2160a.dtsi')
| -rw-r--r-- | arch/arm/dts/fsl-lx2160a.dtsi | 57 |
1 files changed, 51 insertions, 6 deletions
diff --git a/arch/arm/dts/fsl-lx2160a.dtsi b/arch/arm/dts/fsl-lx2160a.dtsi index dee1e2f215..bfdf178738 100644 --- a/arch/arm/dts/fsl-lx2160a.dtsi +++ b/arch/arm/dts/fsl-lx2160a.dtsi @@ -43,6 +43,12 @@ interrupts = <1 9 0x4>; }; + gic_lpi_base: syscon@0x80000000 { + compatible = "gic-lpi-base"; + reg = <0x0 0x80000000 0x0 0x200000>; + max-gic-redistributors = <16>; + }; + timer { compatible = "arm,armv8-timer"; interrupts = <1 13 0x8>, /* Physical Secure PPI, active-low */ @@ -193,6 +199,28 @@ num-cs = <6>; }; + gpio0: gpio@2300000 { + compatible = "fsl,qoriq-gpio"; + reg = <0x0 0x2300000 0x0 0x10000>; + interrupts = <0 36 4>; + gpio-controller; + little-endian; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio1: gpio@2310000 { + compatible = "fsl,qoriq-gpio"; + reg = <0x0 0x2310000 0x0 0x10000>; + interrupts = <0 36 4>; + gpio-controller; + little-endian; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + gpio2: gpio@2320000 { compatible = "fsl,qoriq-gpio"; reg = <0x0 0x2320000 0x0 0x10000>; @@ -204,6 +232,17 @@ #interrupt-cells = <2>; }; + gpio3: gpio@2330000 { + compatible = "fsl,qoriq-gpio"; + reg = <0x0 0x2330000 0x0 0x10000>; + interrupts = <0 37 4>; + gpio-controller; + little-endian; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + watchdog@23a0000 { compatible = "arm,sbsa-gwdt"; reg = <0x0 0x23a0000 0 0x1000>, @@ -297,7 +336,8 @@ #size-cells = <2>; device_type = "pci"; bus-range = <0x0 0xff>; - ranges = <0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>; + ranges = <0x81000000 0x0 0x00000000 0x80 0x00020000 0x0 0x00010000 /* downstream I/O */ + 0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ }; pcie@3500000 { @@ -312,7 +352,8 @@ device_type = "pci"; num-lanes = <2>; bus-range = <0x0 0xff>; - ranges = <0x82000000 0x0 0x40000000 0x88 0x40000000 0x0 0x40000000>; + ranges = <0x81000000 0x0 0x00000000 0x88 0x00020000 0x0 0x00010000 /* downstream I/O */ + 0x82000000 0x0 0x40000000 0x88 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ }; pcie@3600000 { @@ -326,7 +367,8 @@ #size-cells = <2>; device_type = "pci"; bus-range = <0x0 0xff>; - ranges = <0x82000000 0x0 0x40000000 0x90 0x40000000 0x0 0x40000000>; + ranges = <0x81000000 0x0 0x00000000 0x90 0x00020000 0x0 0x00010000 /* downstream I/O */ + 0x82000000 0x0 0x40000000 0x90 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ }; pcie@3700000 { @@ -340,7 +382,8 @@ #size-cells = <2>; device_type = "pci"; bus-range = <0x0 0xff>; - ranges = <0x82000000 0x0 0x40000000 0x98 0x40000000 0x0 0x40000000>; + ranges = <0x81000000 0x0 0x00000000 0x98 0x00020000 0x0 0x00010000 /* downstream I/O */ + 0x82000000 0x0 0x40000000 0x98 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ }; pcie@3800000 { @@ -354,7 +397,8 @@ #size-cells = <2>; device_type = "pci"; bus-range = <0x0 0xff>; - ranges = <0x82000000 0x0 0x40000000 0xa0 0x40000000 0x0 0x40000000>; + ranges = <0x81000000 0x0 0x00000000 0xa0 0x00020000 0x0 0x00010000 /* downstream I/O */ + 0x82000000 0x0 0x40000000 0xa0 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ }; pcie@3900000 { @@ -368,7 +412,8 @@ #size-cells = <2>; device_type = "pci"; bus-range = <0x0 0xff>; - ranges = <0x82000000 0x0 0x40000000 0xa8 0x40000000 0x0 0x40000000>; + ranges = <0x81000000 0x0 0x00000000 0xa8 0x00020000 0x0 0x00010000 /* downstream I/O */ + 0x82000000 0x0 0x40000000 0xa8 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ }; fsl_mc: fsl-mc@80c000000 { |