diff options
| author | Hou Zhiqiang <Zhiqiang.Hou@nxp.com> | 2019-04-08 10:15:58 +0000 |
|---|---|---|
| committer | Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> | 2019-05-22 12:24:24 +0530 |
| commit | a8d6050543428caa67a61351828f677945beafc6 (patch) | |
| tree | 0526c3ff5f8508651e90e508df67185ff3734dd9 /arch/arm/dts/fsl-lx2160a.dtsi | |
| parent | 1d341bc4b6b357e7348ab4393247e369aeb30aa6 (diff) | |
armv8: lx2160a: add PCIe controller DT nodes
The LX2160A integrated 6 PCIe Gen4 controllers.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Diffstat (limited to 'arch/arm/dts/fsl-lx2160a.dtsi')
| -rw-r--r-- | arch/arm/dts/fsl-lx2160a.dtsi | 85 |
1 files changed, 85 insertions, 0 deletions
diff --git a/arch/arm/dts/fsl-lx2160a.dtsi b/arch/arm/dts/fsl-lx2160a.dtsi index 510b070582..28220781d3 100644 --- a/arch/arm/dts/fsl-lx2160a.dtsi +++ b/arch/arm/dts/fsl-lx2160a.dtsi @@ -176,4 +176,89 @@ status = "disabled"; }; + + pcie@3400000 { + compatible = "fsl,lx2160a-pcie"; + reg = <0x00 0x03400000 0x0 0x80000 /* PAB registers */ + 0x00 0x03480000 0x0 0x40000 /* LUT registers */ + 0x00 0x034c0000 0x0 0x40000 /* PF control registers */ + 0x80 0x00000000 0x0 0x1000>; /* configuration space */ + reg-names = "ccsr", "lut", "pf_ctrl", "config"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + bus-range = <0x0 0xff>; + ranges = <0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>; + }; + + pcie@3500000 { + compatible = "fsl,lx2160a-pcie"; + reg = <0x00 0x03500000 0x0 0x80000 /* PAB registers */ + 0x00 0x03580000 0x0 0x40000 /* LUT registers */ + 0x00 0x035c0000 0x0 0x40000 /* PF control registers */ + 0x88 0x00000000 0x0 0x1000>; /* configuration space */ + reg-names = "ccsr", "lut", "pf_ctrl", "config"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + num-lanes = <2>; + bus-range = <0x0 0xff>; + ranges = <0x82000000 0x0 0x40000000 0x88 0x40000000 0x0 0x40000000>; + }; + + pcie@3600000 { + compatible = "fsl,lx2160a-pcie"; + reg = <0x00 0x03600000 0x0 0x80000 /* PAB registers */ + 0x00 0x03680000 0x0 0x40000 /* LUT registers */ + 0x00 0x036c0000 0x0 0x40000 /* PF control registers */ + 0x90 0x00000000 0x0 0x1000>; /* configuration space */ + reg-names = "ccsr", "lut", "pf_ctrl", "config"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + bus-range = <0x0 0xff>; + ranges = <0x82000000 0x0 0x40000000 0x90 0x40000000 0x0 0x40000000>; + }; + + pcie@3700000 { + compatible = "fsl,lx2160a-pcie"; + reg = <0x00 0x03700000 0x0 0x80000 /* PAB registers */ + 0x00 0x03780000 0x0 0x40000 /* LUT registers */ + 0x00 0x037c0000 0x0 0x40000 /* PF control registers */ + 0x98 0x00000000 0x0 0x1000>; /* configuration space */ + reg-names = "ccsr", "lut", "pf_ctrl", "config"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + bus-range = <0x0 0xff>; + ranges = <0x82000000 0x0 0x40000000 0x98 0x40000000 0x0 0x40000000>; + }; + + pcie@3800000 { + compatible = "fsl,lx2160a-pcie"; + reg = <0x00 0x03800000 0x0 0x80000 /* PAB registers */ + 0x00 0x03880000 0x0 0x40000 /* LUT registers */ + 0x00 0x038c0000 0x0 0x40000 /* PF control registers */ + 0xa0 0x00000000 0x0 0x1000>; /* configuration space */ + reg-names = "ccsr", "lut", "pf_ctrl", "config"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + bus-range = <0x0 0xff>; + ranges = <0x82000000 0x0 0x40000000 0xa0 0x40000000 0x0 0x40000000>; + }; + + pcie@3900000 { + compatible = "fsl,lx2160a-pcie"; + reg = <0x00 0x03900000 0x0 0x80000 /* PAB registers */ + 0x00 0x03980000 0x0 0x40000 /* LUT registers */ + 0x00 0x039c0000 0x0 0x40000 /* PF control registers */ + 0xa8 0x00000000 0x0 0x1000>; /* configuration space */ + reg-names = "ccsr", "lut", "pf_ctrl", "config"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + bus-range = <0x0 0xff>; + ranges = <0x82000000 0x0 0x40000000 0xa8 0x40000000 0x0 0x40000000>; + }; }; |