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authorJagan Teki <jagan@amarulasolutions.com>2019-12-21 13:24:30 +0530
committerJagan Teki <jagan@amarulasolutions.com>2019-12-27 17:47:26 +0530
commitdbbdc81c6064b4cb7ffc796b71713a19488a2c4c (patch)
tree5a8bba42bdc7677b73ae4565f12a9e7ee454e903 /arch/arm/dts/k3-am654-ddr.dtsi
parentcb56caacf8113cef90a3b477f08912260fd6a02e (diff)
spi: rk: Limit transfers to (64K - 1) bytes
The Rockchip SPI controller's length register only supports 16-bits, yielding a maximum length of 64KiB (the CTRLR1 register holds "length - 1"). Trying to transfer more than that (e.g., with a large SPI flash read) will cause the driver to hang. Now, it seems that while theoretically we should be able to program CTRLR1 with 0xffff, and get a 64KiB transfer, but that also seems to cause the core to choke, so stick with a maximum of 64K - 1 bytes -- i.e., 0xffff. Note, that the size is further divided into 'minus 1' while writing into CTRLR1. This change fixed two different read issues, 1. sf read failure when with > 0x10000 2. Boot from SPI flash failed during spi_flash_read call in common/spl/spl_spi.c Observed and Tested in - Rockpro64 with Gigadevice flash - ROC-RK3399-PC with Winbond flash Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
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