diff options
author | Lokesh Vutla <lokeshvutla@ti.com> | 2019-09-04 16:01:40 +0530 |
---|---|---|
committer | Tom Rini <trini@konsulko.com> | 2019-10-11 10:07:35 -0400 |
commit | 1b846fc24d80ceb358312b4aa3e8242d36784fe4 (patch) | |
tree | 6cf30c962115b9238747b63b55ac964235ca4cff /arch/arm/dts/k3-j721e-common-proc-board.dts | |
parent | 293e39780d5f03c3ce8a2b032b607a9cf161d9fc (diff) |
arm: dts: k3-j721e-main: Add C71x DSP node
The J721E SoCs have a single TMS320C71x DSP Subsystem in the MAIN
voltage domain containing the next-generation C711 CPU core. The
subsystem has 32 KB of L1D configurable SRAM/Cache and 512 KB of
L2 configurable SRAM/Cache. This subsystem has a CMMU but is not
used currently. The inter-processor communication between the main
A72 cores and the C711 processor is achieved through shared memory
and a Mailbox. Add the DT node for this DSP processor sub-system
in the common k3-j721e-main.dtsi file.
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Diffstat (limited to 'arch/arm/dts/k3-j721e-common-proc-board.dts')
-rw-r--r-- | arch/arm/dts/k3-j721e-common-proc-board.dts | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm/dts/k3-j721e-common-proc-board.dts b/arch/arm/dts/k3-j721e-common-proc-board.dts index a548277718..b21f597a80 100644 --- a/arch/arm/dts/k3-j721e-common-proc-board.dts +++ b/arch/arm/dts/k3-j721e-common-proc-board.dts @@ -22,6 +22,7 @@ remoteproc5 = &main_r5fss1_core1; remoteproc6 = &c66_0; remoteproc7 = &c66_1; + remoteproc8 = &c71_0; }; }; |