diff options
| author | Jagan Teki <jagan@amarulasolutions.com> | 2019-07-15 23:58:56 +0530 |
|---|---|---|
| committer | Kever Yang <kever.yang@rock-chips.com> | 2019-07-20 23:59:44 +0800 |
| commit | 9a7b8db9f081ce8eb30da046cbab6d23c41c2ebc (patch) | |
| tree | e8e042bf58fc54d9d25f08e669a7add08781870d /arch/arm/dts/logicpd-som-lv.dtsi | |
| parent | a153b034df221c5fa803c07293f7544930e7a37f (diff) | |
rockchip: dts: rk3399: nanopi-neo4: Use DDR3-1866 dtsi
Use DDR3-1866 2GB ddr timings dtsi for 1GB NanoPi Neo4 board.
Since sdram rk3399 support dynamic stride and rank detection it
can able to detect 1GB ddr eventough the timings are meant for
dual channel, 2GB size.
Bootchain after and before this change are:
TPL -> SPL -> U-Boot proper
rkbin -> SPL -> U-Boot proper
This certainly fix the second channel data training initialization
since we have dynamic rank, stride where second channel capabilities
are clear or memset to 0.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
Diffstat (limited to 'arch/arm/dts/logicpd-som-lv.dtsi')
0 files changed, 0 insertions, 0 deletions