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authorEric Gao <eric.gao@rock-chips.com>2017-05-02 18:32:45 +0800
committerSimon Glass <sjg@chromium.org>2017-05-10 13:37:22 -0600
commit2085de57f3928d72b27338f68d4250d1fb302d04 (patch)
treeed3f69cc00a3232a9a624f11b0c3a34e65599113 /arch/arm/dts/rk3288.dtsi
parent9b534ba001cdfc54f8076cf8fa1165d4ad108abf (diff)
rockchip: dts: evb_rk3288: Add mipi display support
Add mipi dsi configuration for evb-rk3288 device tree. Signed-off-by: Eric Gao <eric.gao@rock-chips.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'arch/arm/dts/rk3288.dtsi')
-rw-r--r--arch/arm/dts/rk3288.dtsi41
1 files changed, 41 insertions, 0 deletions
diff --git a/arch/arm/dts/rk3288.dtsi b/arch/arm/dts/rk3288.dtsi
index bcf051a9d9..64aa07de36 100644
--- a/arch/arm/dts/rk3288.dtsi
+++ b/arch/arm/dts/rk3288.dtsi
@@ -664,6 +664,7 @@
};
vopb: vop@ff930000 {
+ u-boot,dm-pre-reloc;
compatible = "rockchip,rk3288-vop";
reg = <0xff930000 0x19c>;
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
@@ -689,6 +690,11 @@
reg = <2>;
remote-endpoint = <&lvds_in_vopb>;
};
+ vopb_out_mipi: endpoint@3 {
+ reg = <3>;
+ remote-endpoint = <&mipi_in_vopb>;
+ };
+
};
};
@@ -729,6 +735,11 @@
reg = <2>;
remote-endpoint = <&lvds_in_vopl>;
};
+ vopl_out_mipi: endpoint@3 {
+ reg = <3>;
+ remote-endpoint = <&mipi_in_vopl>;
+ };
+
};
};
@@ -823,6 +834,36 @@
};
};
+ mipi_dsi0: mipi@ff960000 {
+ compatible = "rockchip,rk3288_mipi_dsi";
+ reg = <0xff960000 0x4000>;
+ clocks = <&cru PCLK_MIPI_DSI0>;
+ clock-names = "pclk_mipi";
+ /*pinctrl-names = "default";
+ pinctrl-0 = <&lcdc0_ctl>;*/
+ rockchip,grf = <&grf>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ mipi_in: port {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ mipi_in_vopb: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&vopb_out_mipi>;
+ };
+ mipi_in_vopl: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&vopl_out_mipi>;
+ };
+ };
+ };
+ };
+
hdmi_audio: hdmi_audio {
compatible = "rockchip,rk3288-hdmi-audio";
i2s-controller = <&i2s>;