diff options
| author | Tom Rini <trini@konsulko.com> | 2017-08-14 10:40:01 -0400 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2017-08-14 10:40:01 -0400 |
| commit | c1b62ba9ca0e41fdd548cb3bb9af3b3f90d4a393 (patch) | |
| tree | 7e653a1823011bfb075540428bfdab96707f1517 /arch/arm/dts/rk3368.dtsi | |
| parent | bc5d0384458466ed5b3608d326eec03cd4f13016 (diff) | |
| parent | 217273cd441fe3d00a1bdad143dcb656854963f9 (diff) | |
Merge branch 'master' of git://git.denx.de/u-boot-rockchip
Diffstat (limited to 'arch/arm/dts/rk3368.dtsi')
| -rw-r--r-- | arch/arm/dts/rk3368.dtsi | 30 |
1 files changed, 22 insertions, 8 deletions
diff --git a/arch/arm/dts/rk3368.dtsi b/arch/arm/dts/rk3368.dtsi index 9daf765430..b4f4f6139d 100644 --- a/arch/arm/dts/rk3368.dtsi +++ b/arch/arm/dts/rk3368.dtsi @@ -46,6 +46,7 @@ #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/pinctrl/rockchip.h> #include <dt-bindings/thermal/thermal.h> +#include <dt-bindings/memory/rk3368-dmc.h> / { compatible = "rockchip,rk3368"; @@ -227,6 +228,21 @@ #clock-cells = <0>; }; + dmc: dmc@ff610000 { + compatible = "rockchip,rk3368-dmc", "syscon"; + rockchip,cru = <&cru>; + rockchip,grf = <&grf>; + rockchip,msch = <&service_msch>; + reg = <0 0xff610000 0 0x400 + 0 0xff620000 0 0x400>; + }; + + service_msch: syscon@ffac0000 { + compatible = "rockchip,rk3368-msch", "syscon"; + reg = <0x0 0xffac0000 0x0 0x2000>; + status = "okay"; + }; + sdmmc: dwmmc@ff0c0000 { compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc"; reg = <0x0 0xff0c0000 0x0 0x4000>; @@ -546,12 +562,6 @@ status = "disabled"; }; - dmc: dmc@ff610000 { - u-boot,dm-pre-reloc; - compatible = "rockchip,rk3368-dmc", "syscon"; - reg = <0x0 0xff610000 0x0 0x1000>; - }; - i2c0: i2c@ff650000 { compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c"; reg = <0x0 0xff650000 0x0 0x1000>; @@ -647,11 +657,15 @@ }; pmugrf: syscon@ff738000 { - u-boot,dm-pre-reloc; compatible = "rockchip,rk3368-pmugrf", "syscon"; reg = <0x0 0xff738000 0x0 0x1000>; }; + sgrf: syscon@ff740000 { + compatible = "rockchip,rk3368-sgrf", "syscon"; + reg = <0x0 0xff740000 0x0 0x1000>; + }; + cru: clock-controller@ff760000 { compatible = "rockchip,rk3368-cru"; reg = <0x0 0xff760000 0x0 0x1000>; @@ -673,7 +687,7 @@ status = "disabled"; }; - timer@ff810000 { + timer0: timer@ff810000 { compatible = "rockchip,rk3368-timer", "rockchip,rk3288-timer"; reg = <0x0 0xff810000 0x0 0x20>; interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; |