diff options
| author | Tom Rini <trini@konsulko.com> | 2017-03-17 09:11:12 -0400 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2017-03-17 14:15:17 -0400 |
| commit | f9515756b6d76cde99b385dda905dfb20d31ea48 (patch) | |
| tree | b2cd0007fb90a43992cb51f1a02d4e191e3dde10 /arch/arm/dts/rk3399.dtsi | |
| parent | e245f1a5db086d676cbd97371046ea5c5e554326 (diff) | |
| parent | 520c174b3564ae183f0e7c118dc8ce3770ae20b0 (diff) | |
Merge git://git.denx.de/u-boot-rockchip
This includes support for rk3188 from Heiko Stübner and and rk3328 from
Kever Yang. Also included is SPL support for rk3399 and a fix for
rk3288 to get it booting again (spl_early_init()).
Diffstat (limited to 'arch/arm/dts/rk3399.dtsi')
| -rw-r--r-- | arch/arm/dts/rk3399.dtsi | 46 |
1 files changed, 46 insertions, 0 deletions
diff --git a/arch/arm/dts/rk3399.dtsi b/arch/arm/dts/rk3399.dtsi index 22277ff0ad..456fdb6198 100644 --- a/arch/arm/dts/rk3399.dtsi +++ b/arch/arm/dts/rk3399.dtsi @@ -24,6 +24,8 @@ serial2 = &uart2; serial3 = &uart3; serial4 = &uart4; + mmc0 = &sdhci; + mmc1 = &sdmmc; }; cpus { @@ -183,6 +185,7 @@ }; sdhci: sdhci@fe330000 { + u-boot,dm-pre-reloc; compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1"; reg = <0x0 0xfe330000 0x0 0x10000>; interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; @@ -416,6 +419,7 @@ }; pmugrf: syscon@ff320000 { + u-boot,dm-pre-reloc; compatible = "rockchip,rk3399-pmugrf", "syscon", "simple-mfd"; reg = <0x0 0xff320000 0x0 0x1000>; #address-cells = <1>; @@ -427,6 +431,12 @@ }; }; + pmusgrf: syscon@ff330000 { + u-boot,dm-pre-reloc; + compatible = "rockchip,rk3399-pmusgrf", "syscon"; + reg = <0x0 0xff330000 0x0 0xe3d4>; + }; + spi3: spi@ff350000 { compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; reg = <0x0 0xff350000 0x0 0x1000>; @@ -497,7 +507,40 @@ status = "disabled"; }; + cic: syscon@ff620000 { + u-boot,dm-pre-reloc; + compatible = "rockchip,rk3399-cic", "syscon"; + reg = <0x0 0xff620000 0x0 0x100>; + }; + + dfi: dfi@ff630000 { + reg = <0x00 0xff630000 0x00 0x4000>; + compatible = "rockchip,rk3399-dfi"; + rockchip,pmu = <&pmugrf>; + clocks = <&cru PCLK_DDR_MON>; + clock-names = "pclk_ddr_mon"; + status = "disabled"; + }; + + dmc: dmc { + u-boot,dm-pre-reloc; + compatible = "rockchip,rk3399-dmc"; + devfreq-events = <&dfi>; + interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru SCLK_DDRCLK>; + clock-names = "dmc_clk"; + reg = <0x0 0xffa80000 0x0 0x0800 + 0x0 0xffa80800 0x0 0x1800 + 0x0 0xffa82000 0x0 0x2000 + 0x0 0xffa84000 0x0 0x1000 + 0x0 0xffa88000 0x0 0x0800 + 0x0 0xffa88800 0x0 0x1800 + 0x0 0xffa8a000 0x0 0x2000 + 0x0 0xffa8c000 0x0 0x1000>; + }; + pmucru: pmu-clock-controller@ff750000 { + u-boot,dm-pre-reloc; compatible = "rockchip,rk3399-pmucru"; reg = <0x0 0xff750000 0x0 0x1000>; #clock-cells = <1>; @@ -507,6 +550,7 @@ }; cru: clock-controller@ff760000 { + u-boot,dm-pre-reloc; compatible = "rockchip,rk3399-cru"; reg = <0x0 0xff760000 0x0 0x1000>; #clock-cells = <1>; @@ -530,6 +574,7 @@ }; grf: syscon@ff770000 { + u-boot,dm-pre-reloc; compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd"; reg = <0x0 0xff770000 0x0 0x10000>; #address-cells = <1>; @@ -607,6 +652,7 @@ }; pinctrl: pinctrl { + u-boot,dm-pre-reloc; compatible = "rockchip,rk3399-pinctrl"; rockchip,grf = <&grf>; rockchip,pmu = <&pmugrf>; |