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| author | Lokesh Vutla <lokeshvutla@ti.com> | 2018-05-03 20:34:49 +0530 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2018-05-06 13:35:40 -0400 |
| commit | 7ce85318cfff5fd82a059131761559cba7fef309 (patch) | |
| tree | 54a9427928027a68a0412c69619ed3b5a4c6fc52 /arch/arm/dts/s5pc100-pinctrl.dtsi | |
| parent | 535adee8692f89df3472f92ae68d6aa0efb883d7 (diff) | |
arm: mach-omap2: cache: Explicitly enable I cache
omap-common cache enabling sequence relies on cpu_init_cp15()
(inside start.S) for enabling I-caches. But cpu_init_cp15()
can be skipped if CONFIG_SKIP_LOWLEVEL_INIT is defined. So
enable I-caches if not enabled already.
Debugged-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Tested-by: Steve Kipisz <s-kipisz2@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Tested-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Diffstat (limited to 'arch/arm/dts/s5pc100-pinctrl.dtsi')
0 files changed, 0 insertions, 0 deletions