diff options
| author | Tudor Ambarus <tudor.ambarus@microchip.com> | 2019-09-27 13:09:19 +0000 |
|---|---|---|
| committer | Eugen Hristev <eugen.hristev@microchip.com> | 2019-10-08 09:16:11 +0300 |
| commit | 228f9e0244960c9823ebcecf3bb0e4e06dc0420f (patch) | |
| tree | 6b96e542257d16cb0003579ff9f8d287dda24363 /arch/arm/dts/sam9x60.dtsi | |
| parent | 8c04ea7cada44f393c435001bc466a82fde04fba (diff) | |
ARM: dts: at91: sam9x60ek: Enable qspi node
The sam9x60 qspi controller uses 2 clocks, one for the peripheral register
access, the other for the qspi core and phy. Both are mandatory.
Enable the qspi node together with the SST26VF064B qspi nor flash
memory. Booting from the QSPI NOR flash is now possible.
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Diffstat (limited to 'arch/arm/dts/sam9x60.dtsi')
| -rw-r--r-- | arch/arm/dts/sam9x60.dtsi | 29 |
1 files changed, 29 insertions, 0 deletions
diff --git a/arch/arm/dts/sam9x60.dtsi b/arch/arm/dts/sam9x60.dtsi index a66d0a278a..9c16ba1e6a 100644 --- a/arch/arm/dts/sam9x60.dtsi +++ b/arch/arm/dts/sam9x60.dtsi @@ -22,6 +22,7 @@ serial0 = &dbgu; gpio0 = &pioA; gpio1 = &pioB; + spi0 = &qspi; }; clocks { @@ -60,6 +61,17 @@ #size-cells = <1>; ranges; + qspi: spi@f0014000 { + compatible = "microchip,sam9x60-qspi"; + reg = <0xf0014000 0x100>, <0x70000000 0x10000000>; + reg-names = "qspi_base", "qspi_mmap"; + clocks = <&qspi_clk>, <&qspick>; + clock-names = "pclk", "qspick"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + macb0: ethernet@f802c000 { compatible = "cdns,sam9x60-macb", "cdns,macb"; reg = <0xf802c000 0x100>; @@ -172,6 +184,18 @@ atmel,clk-divisors = <1 2 4 6>; }; + system: systemck { + compatible = "atmel,at91rm9200-clk-system"; + #address-cells = <1>; + #size-cells = <0>; + + qspick: qspick { + #clock-cells = <0>; + reg = <19>; + clocks = <&mck>; + }; + }; + periph: periphck { compatible = "microchip,sam9x60-clk-peripheral"; #address-cells = <1>; @@ -202,6 +226,11 @@ #clock-cells = <0>; reg = <24>; }; + + qspi_clk: qspi_clk { + #clock-cells = <0>; + reg = <35>; + }; }; generic: gck { |