summaryrefslogtreecommitdiff
path: root/arch/arm/dts/socfpga_arria10-u-boot.dtsi
diff options
context:
space:
mode:
authorLey Foon Tan <ley.foon.tan@intel.com>2020-04-07 15:43:12 +0800
committerMarek Vasut <marex@denx.de>2020-04-13 13:49:51 +0200
commitf3fccb12c02c429fef64bb26714ada0461096538 (patch)
treea89998944924a278da14830bf0f01d8967bfd71a /arch/arm/dts/socfpga_arria10-u-boot.dtsi
parent8876f89640d3386822025f42b60b1ff9dd679123 (diff)
arm: dts: arria10: Move uboot specific properties to u-boot.dtsi
Move Uboot specific properties to *u-boot.dtsi files. Preparation to sync Arria 10 device tree from Linux. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Diffstat (limited to 'arch/arm/dts/socfpga_arria10-u-boot.dtsi')
-rw-r--r--arch/arm/dts/socfpga_arria10-u-boot.dtsi123
1 files changed, 123 insertions, 0 deletions
diff --git a/arch/arm/dts/socfpga_arria10-u-boot.dtsi b/arch/arm/dts/socfpga_arria10-u-boot.dtsi
new file mode 100644
index 0000000000..c637b10073
--- /dev/null
+++ b/arch/arm/dts/socfpga_arria10-u-boot.dtsi
@@ -0,0 +1,123 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2014, 2020, Intel Corporation
+ */
+
+/ {
+ chosen {
+ tick-timer = &timer2;
+ u-boot,dm-pre-reloc;
+ };
+
+ memory@0 {
+ u-boot,dm-pre-reloc;
+ };
+
+ soc {
+ u-boot,dm-pre-reloc;
+ };
+};
+
+&clkmgr {
+ u-boot,dm-pre-reloc;
+
+ clocks {
+ u-boot,dm-pre-reloc;
+ };
+};
+
+&cb_intosc_hs_div2_clk {
+ u-boot,dm-pre-reloc;
+};
+
+&cb_intosc_ls_clk {
+ u-boot,dm-pre-reloc;
+};
+
+&f2s_free_clk {
+ u-boot,dm-pre-reloc;
+};
+
+&i2c0 {
+ reset-names = "i2c";
+};
+
+&i2c1 {
+ reset-names = "i2c";
+};
+
+&i2c2 {
+ reset-names = "i2c";
+};
+
+&i2c3 {
+ reset-names = "i2c";
+};
+
+&i2c4 {
+ reset-names = "i2c";
+};
+
+&l4_mp_clk {
+ u-boot,dm-pre-reloc;
+};
+
+&l4_sp_clk {
+ u-boot,dm-pre-reloc;
+};
+
+&l4_sys_free_clk {
+ u-boot,dm-pre-reloc;
+};
+
+&main_periph_ref_clk {
+ u-boot,dm-pre-reloc;
+};
+
+&main_pll {
+ u-boot,dm-pre-reloc;
+};
+
+&main_noc_base_clk {
+ u-boot,dm-pre-reloc;
+};
+
+&noc_free_clk {
+ u-boot,dm-pre-reloc;
+};
+
+&osc1 {
+ u-boot,dm-pre-reloc;
+};
+
+&peri_noc_base_clk {
+ u-boot,dm-pre-reloc;
+};
+
+&periph_pll {
+ u-boot,dm-pre-reloc;
+};
+
+&porta {
+ bank-name = "porta";
+};
+
+&portb {
+ bank-name = "portb";
+};
+
+&portc {
+ bank-name = "portc";
+};
+
+&rst {
+ u-boot,dm-pre-reloc;
+};
+
+&sysmgr {
+ u-boot,dm-pre-reloc;
+};
+
+&timer2 {
+ u-boot,dm-pre-reloc;
+};