ARM: socfpga: Synchronize Arria10 DTs

Synchronize Altera Arria 10 DT sources with Linux 4.16.3 as of commit
ef8216d28a5920022cddcb694d2d75bd1f0035ca

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>

1 files changed, 292 insertions, 302 deletions

diff --git a/arch/arm/dts/socfpga_arria10.dtsi b/arch/arm/dts/socfpga_arria10.dtsi
index abfd0bc4f8..b51febda9c 100644
--- a/arch/arm/dts/socfpga_arria10.dtsi
+++ b/arch/arm/dts/socfpga_arria10.dtsi
@@ -1,5 +1,5 @@
 /*
- * Copyright Altera Corporation (C) 2014-2017. All rights reserved.
+ * Copyright Altera Corporation (C) 2014. All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms and conditions of the GNU General Public License,
@@ -14,7 +14,6 @@
  * this program.  If not, see <http://www.gnu.org/licenses/>.
  */
 
-#include "skeleton.dtsi"
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/reset/altr,rst-mgr-a10.h>
 
@@ -22,29 +21,10 @@
 	#address-cells = <1>;
 	#size-cells = <1>;
 
-	aliases {
-		ethernet0 = &gmac0;
-		ethernet1 = &gmac1;
-		ethernet2 = &gmac2;
-		serial0 = &uart0;
-		serial1 = &uart1;
-		timer0 = &timer0;
-		timer1 = &timer1;
-		timer2 = &timer2;
-		timer3 = &timer3;
-		spi0 = &spi0;
-		spi1 = &spi1;
-	};
-
-	memory {
-		name = "memory";
-		device_type = "memory";
-		reg = <0x0 0x40000000>; /* 1GB */
-	};
-
 	cpus {
 		#address-cells = <1>;
 		#size-cells = <0>;
+		enable-method = "altr,socfpga-a10-smp";
 
 		cpu@0 {
 			compatible = "arm,cortex-a9";
@@ -102,321 +82,335 @@
 			};
 		};
 
-		clkmgr@ffd04000 {
-			compatible = "altr,clk-mgr";
-			reg = <0xffd04000 0x1000>;
-			reg-names = "soc_clock_manager_OCP_SLV";
-
-			clocks {
-				#address-cells = <1>;
-				#size-cells = <0>;
-
-				cb_intosc_hs_div2_clk: cb_intosc_hs_div2_clk {
-					#clock-cells = <0>;
-					compatible = "fixed-clock";
-				};
-
-				cb_intosc_ls_clk: cb_intosc_ls_clk {
-					#clock-cells = <0>;
-					compatible = "fixed-clock";
-				};
+		base_fpga_region {
+			#address-cells = <0x1>;
+			#size-cells = <0x1>;
 
-				f2s_free_clk: f2s_free_clk {
-					#clock-cells = <0>;
-					compatible = "fixed-clock";
-				};
+			compatible = "fpga-region";
+			fpga-mgr = <&fpga_mgr>;
+		};
 
-				osc1: osc1 {
-					#clock-cells = <0>;
-					compatible = "fixed-clock";
-				};
+		clkmgr@ffd04000 {
+				compatible = "altr,clk-mgr";
+				reg = <0xffd04000 0x1000>;
 
-				main_pll: main_pll {
+				clocks {
 					#address-cells = <1>;
 					#size-cells = <0>;
-					#clock-cells = <0>;
-					compatible = "altr,socfpga-a10-pll-clock";
-					clocks = <&osc1>, <&cb_intosc_ls_clk>,
-							 <&f2s_free_clk>;
-					reg = <0x40>;
 
-					main_mpu_base_clk: main_mpu_base_clk {
+					cb_intosc_hs_div2_clk: cb_intosc_hs_div2_clk {
 						#clock-cells = <0>;
-						compatible = "altr,socfpga-a10-perip-clk";
-						clocks = <&main_pll>;
-						div-reg = <0x140 0 11>;
+						compatible = "fixed-clock";
 					};
 
-					main_noc_base_clk: main_noc_base_clk {
+					cb_intosc_ls_clk: cb_intosc_ls_clk {
 						#clock-cells = <0>;
-						compatible = "altr,socfpga-a10-perip-clk";
-						clocks = <&main_pll>;
-						div-reg = <0x144 0 11>;
+						compatible = "fixed-clock";
 					};
 
-					main_emaca_clk: main_emaca_clk {
+					f2s_free_clk: f2s_free_clk {
 						#clock-cells = <0>;
-						compatible = "altr,socfpga-a10-perip-clk";
-						clocks = <&main_pll>;
-						reg = <0x68>;
+						compatible = "fixed-clock";
 					};
 
-					main_emacb_clk: main_emacb_clk {
+					osc1: osc1 {
 						#clock-cells = <0>;
-						compatible = "altr,socfpga-a10-perip-clk";
-						clocks = <&main_pll>;
-						reg = <0x6C>;
+						compatible = "fixed-clock";
 					};
 
-					main_emac_ptp_clk: main_emac_ptp_clk {
+					main_pll: main_pll@40 {
+						#address-cells = <1>;
+						#size-cells = <0>;
 						#clock-cells = <0>;
-						compatible = "altr,socfpga-a10-perip-clk";
-						clocks = <&main_pll>;
-						reg = <0x70>;
+						compatible = "altr,socfpga-a10-pll-clock";
+						clocks = <&osc1>, <&cb_intosc_ls_clk>,
+							 <&f2s_free_clk>;
+						reg = <0x40>;
+
+						main_mpu_base_clk: main_mpu_base_clk {
+							#clock-cells = <0>;
+							compatible = "altr,socfpga-a10-perip-clk";
+							clocks = <&main_pll>;
+							div-reg = <0x140 0 11>;
+						};
+
+						main_noc_base_clk: main_noc_base_clk {
+							#clock-cells = <0>;
+							compatible = "altr,socfpga-a10-perip-clk";
+							clocks = <&main_pll>;
+							div-reg = <0x144 0 11>;
+						};
+
+						main_emaca_clk: main_emaca_clk@68 {
+							#clock-cells = <0>;
+							compatible = "altr,socfpga-a10-perip-clk";
+							clocks = <&main_pll>;
+							reg = <0x68>;
+						};
+
+						main_emacb_clk: main_emacb_clk@6c {
+							#clock-cells = <0>;
+							compatible = "altr,socfpga-a10-perip-clk";
+							clocks = <&main_pll>;
+							reg = <0x6C>;
+						};
+
+						main_emac_ptp_clk: main_emac_ptp_clk@70 {
+							#clock-cells = <0>;
+							compatible = "altr,socfpga-a10-perip-clk";
+							clocks = <&main_pll>;
+							reg = <0x70>;
+						};
+
+						main_gpio_db_clk: main_gpio_db_clk@74 {
+							#clock-cells = <0>;
+							compatible = "altr,socfpga-a10-perip-clk";
+							clocks = <&main_pll>;
+							reg = <0x74>;
+						};
+
+						main_sdmmc_clk: main_sdmmc_clk@78 {
+							#clock-cells = <0>;
+							compatible = "altr,socfpga-a10-perip-clk"
+;
+							clocks = <&main_pll>;
+							reg = <0x78>;
+						};
+
+						main_s2f_usr0_clk: main_s2f_usr0_clk@7c {
+							#clock-cells = <0>;
+							compatible = "altr,socfpga-a10-perip-clk";
+							clocks = <&main_pll>;
+							reg = <0x7C>;
+						};
+
+						main_s2f_usr1_clk: main_s2f_usr1_clk@80 {
+							#clock-cells = <0>;
+							compatible = "altr,socfpga-a10-perip-clk";
+							clocks = <&main_pll>;
+							reg = <0x80>;
+						};
+
+						main_hmc_pll_ref_clk: main_hmc_pll_ref_clk@84 {
+							#clock-cells = <0>;
+							compatible = "altr,socfpga-a10-perip-clk";
+							clocks = <&main_pll>;
+							reg = <0x84>;
+						};
+
+						main_periph_ref_clk: main_periph_ref_clk@9c {
+							#clock-cells = <0>;
+							compatible = "altr,socfpga-a10-perip-clk";
+							clocks = <&main_pll>;
+							reg = <0x9C>;
+						};
 					};
 
-					main_gpio_db_clk: main_gpio_db_clk {
+					periph_pll: periph_pll@c0 {
+						#address-cells = <1>;
+						#size-cells = <0>;
 						#clock-cells = <0>;
-						compatible = "altr,socfpga-a10-perip-clk";
-						clocks = <&main_pll>;
-						reg = <0x74>;
+						compatible = "altr,socfpga-a10-pll-clock";
+						clocks = <&osc1>, <&cb_intosc_ls_clk>,
+							 <&f2s_free_clk>, <&main_periph_ref_clk>;
+						reg = <0xC0>;
+
+						peri_mpu_base_clk: peri_mpu_base_clk {
+							#clock-cells = <0>;
+							compatible = "altr,socfpga-a10-perip-clk";
+							clocks = <&periph_pll>;
+							div-reg = <0x140 16 11>;
+						};
+
+						peri_noc_base_clk: peri_noc_base_clk {
+							#clock-cells = <0>;
+							compatible = "altr,socfpga-a10-perip-clk";
+							clocks = <&periph_pll>;
+							div-reg = <0x144 16 11>;
+						};
+
+						peri_emaca_clk: peri_emaca_clk@e8 {
+							#clock-cells = <0>;
+							compatible = "altr,socfpga-a10-perip-clk";
+							clocks = <&periph_pll>;
+							reg = <0xE8>;
+						};
+
+						peri_emacb_clk: peri_emacb_clk@ec {
+							#clock-cells = <0>;
+							compatible = "altr,socfpga-a10-perip-clk";
+							clocks = <&periph_pll>;
+							reg = <0xEC>;
+						};
+
+						peri_emac_ptp_clk: peri_emac_ptp_clk@f0 {
+							#clock-cells = <0>;
+							compatible = "altr,socfpga-a10-perip-clk";
+							clocks = <&periph_pll>;
+							reg = <0xF0>;
+						};
+
+						peri_gpio_db_clk: peri_gpio_db_clk@f4 {
+							#clock-cells = <0>;
+							compatible = "altr,socfpga-a10-perip-clk";
+							clocks = <&periph_pll>;
+							reg = <0xF4>;
+						};
+
+						peri_sdmmc_clk: peri_sdmmc_clk@f8 {
+							#clock-cells = <0>;
+							compatible = "altr,socfpga-a10-perip-clk";
+							clocks = <&periph_pll>;
+							reg = <0xF8>;
+						};
+
+						peri_s2f_usr0_clk: peri_s2f_usr0_clk@fc {
+							#clock-cells = <0>;
+							compatible = "altr,socfpga-a10-perip-clk";
+							clocks = <&periph_pll>;
+							reg = <0xFC>;
+						};
+
+						peri_s2f_usr1_clk: peri_s2f_usr1_clk@100 {
+							#clock-cells = <0>;
+							compatible = "altr,socfpga-a10-perip-clk";
+							clocks = <&periph_pll>;
+							reg = <0x100>;
+						};
+
+						peri_hmc_pll_ref_clk: peri_hmc_pll_ref_clk@104 {
+							#clock-cells = <0>;
+							compatible = "altr,socfpga-a10-perip-clk";
+							clocks = <&periph_pll>;
+							reg = <0x104>;
+						};
 					};
 
-					main_sdmmc_clk: main_sdmmc_clk {
+					mpu_free_clk: mpu_free_clk@60 {
 						#clock-cells = <0>;
 						compatible = "altr,socfpga-a10-perip-clk";
-						clocks = <&main_pll>;
-						reg = <0x78>;
+						clocks = <&main_mpu_base_clk>, <&peri_mpu_base_clk>,
+							 <&osc1>, <&cb_intosc_hs_div2_clk>,
+							 <&f2s_free_clk>;
+						reg = <0x60>;
 					};
 
-					main_s2f_usr0_clk: main_s2f_usr0_clk {
+					noc_free_clk: noc_free_clk@64 {
 						#clock-cells = <0>;
 						compatible = "altr,socfpga-a10-perip-clk";
-						clocks = <&main_pll>;
-						reg = <0x7C>;
+						clocks = <&main_noc_base_clk>, <&peri_noc_base_clk>,
+							 <&osc1>, <&cb_intosc_hs_div2_clk>,
+							 <&f2s_free_clk>;
+						reg = <0x64>;
 					};
 
-					main_s2f_usr1_clk: main_s2f_usr1_clk {
+					s2f_user1_free_clk: s2f_user1_free_clk@104 {
 						#clock-cells = <0>;
 						compatible = "altr,socfpga-a10-perip-clk";
-						clocks = <&main_pll>;
-						reg = <0x80>;
+						clocks = <&main_s2f_usr1_clk>, <&peri_s2f_usr1_clk>,
+							 <&osc1>, <&cb_intosc_hs_div2_clk>,
+							 <&f2s_free_clk>;
+						reg = <0x104>;
 					};
 
-					main_hmc_pll_ref_clk: main_hmc_pll_ref_clk {
+					sdmmc_free_clk: sdmmc_free_clk@f8 {
 						#clock-cells = <0>;
 						compatible = "altr,socfpga-a10-perip-clk";
-						clocks = <&main_pll>;
-						reg = <0x84>;
+						clocks = <&main_sdmmc_clk>, <&peri_sdmmc_clk>,
+							 <&osc1>, <&cb_intosc_hs_div2_clk>,
+							 <&f2s_free_clk>;
+						fixed-divider = <4>;
+						reg = <0xF8>;
 					};
 
-					main_periph_ref_clk: main_periph_ref_clk {
+					l4_sys_free_clk: l4_sys_free_clk {
 						#clock-cells = <0>;
 						compatible = "altr,socfpga-a10-perip-clk";
-						clocks = <&main_pll>;
-						reg = <0x9C>;
+						clocks = <&noc_free_clk>;
+						fixed-divider = <4>;
 					};
-				};
-
-				periph_pll: periph_pll {
-					#address-cells = <1>;
-					#size-cells = <0>;
-					#clock-cells = <0>;
-					compatible = "altr,socfpga-a10-pll-clock";
-					clocks = <&osc1>, <&cb_intosc_ls_clk>,
-							 <&f2s_free_clk>, <&main_periph_ref_clk>;
-					reg = <0xC0>;
 
-					peri_mpu_base_clk: peri_mpu_base_clk {
+					l4_main_clk: l4_main_clk {
 						#clock-cells = <0>;
-						compatible = "altr,socfpga-a10-perip-clk";
-						clocks = <&periph_pll>;
-						div-reg = <0x140 16 11>;
+						compatible = "altr,socfpga-a10-gate-clk";
+						clocks = <&noc_free_clk>;
+						div-reg = <0xA8 0 2>;
+						clk-gate = <0x48 1>;
 					};
 
-					peri_noc_base_clk: peri_noc_base_clk {
+					l4_mp_clk: l4_mp_clk {
 						#clock-cells = <0>;
-						compatible = "altr,socfpga-a10-perip-clk";
-						clocks = <&periph_pll>;
-						div-reg = <0x144 16 11>;
+						compatible = "altr,socfpga-a10-gate-clk";
+						clocks = <&noc_free_clk>;
+						div-reg = <0xA8 8 2>;
+						clk-gate = <0x48 2>;
 					};
 
-					peri_emaca_clk: peri_emaca_clk {
+					l4_sp_clk: l4_sp_clk {
 						#clock-cells = <0>;
-						compatible = "altr,socfpga-a10-perip-clk";
-						clocks = <&periph_pll>;
-						reg = <0xE8>;
+						compatible = "altr,socfpga-a10-gate-clk";
+						clocks = <&noc_free_clk>;
+						div-reg = <0xA8 16 2>;
+						clk-gate = <0x48 3>;
 					};
 
-					peri_emacb_clk: peri_emacb_clk {
+					mpu_periph_clk: mpu_periph_clk {
 						#clock-cells = <0>;
-						compatible = "altr,socfpga-a10-perip-clk";
-						clocks = <&periph_pll>;
-						reg = <0xEC>;
+						compatible = "altr,socfpga-a10-gate-clk";
+						clocks = <&mpu_free_clk>;
+						fixed-divider = <4>;
+						clk-gate = <0x48 0>;
 					};
 
-					peri_emac_ptp_clk: peri_emac_ptp_clk {
+					sdmmc_clk: sdmmc_clk {
 						#clock-cells = <0>;
-						compatible = "altr,socfpga-a10-perip-clk";
-						clocks = <&periph_pll>;
-						reg = <0xF0>;
+						compatible = "altr,socfpga-a10-gate-clk";
+						clocks = <&sdmmc_free_clk>;
+						clk-gate = <0xC8 5>;
+						clk-phase = <0 135>;
 					};
 
-					peri_gpio_db_clk: peri_gpio_db_clk {
+					qspi_clk: qspi_clk {
 						#clock-cells = <0>;
-						compatible = "altr,socfpga-a10-perip-clk";
-						clocks = <&periph_pll>;
-						reg = <0xF4>;
+						compatible = "altr,socfpga-a10-gate-clk";
+						clocks = <&l4_main_clk>;
+						clk-gate = <0xC8 11>;
 					};
 
-					peri_sdmmc_clk: peri_sdmmc_clk {
+					nand_clk: nand_clk {
 						#clock-cells = <0>;
-						compatible = "altr,socfpga-a10-perip-clk";
-						clocks = <&periph_pll>;
-						reg = <0xF8>;
+						compatible = "altr,socfpga-a10-gate-clk";
+						clocks = <&l4_mp_clk>;
+						clk-gate = <0xC8 10>;
 					};
 
-					peri_s2f_usr0_clk: peri_s2f_usr0_clk {
+					spi_m_clk: spi_m_clk {
 						#clock-cells = <0>;
-						compatible = "altr,socfpga-a10-perip-clk";
-						clocks = <&periph_pll>;
-						reg = <0xFC>;
+						compatible = "altr,socfpga-a10-gate-clk";
+						clocks = <&l4_main_clk>;
+						clk-gate = <0xC8 9>;
 					};
 
-					peri_s2f_usr1_clk: peri_s2f_usr1_clk {
+					usb_clk: usb_clk {
 						#clock-cells = <0>;
-						compatible = "altr,socfpga-a10-perip-clk";
-						clocks = <&periph_pll>;
-						reg = <0x100>;
+						compatible = "altr,socfpga-a10-gate-clk";
+						clocks = <&l4_mp_clk>;
+						clk-gate = <0xC8 8>;
 					};
 
-					peri_hmc_pll_ref_clk: peri_hmc_pll_ref_clk {
+					s2f_usr1_clk: s2f_usr1_clk {
 						#clock-cells = <0>;
-						compatible = "altr,socfpga-a10-perip-clk";
-						clocks = <&periph_pll>;
-						reg = <0x104>;
+						compatible = "altr,socfpga-a10-gate-clk";
+						clocks = <&peri_s2f_usr1_clk>;
+						clk-gate = <0xC8 6>;
 					};
 				};
+		};
 
-				mpu_free_clk: mpu_free_clk {
-					#clock-cells = <0>;
-					compatible = "altr,socfpga-a10-perip-clk";
-					clocks = <&main_mpu_base_clk>, <&peri_mpu_base_clk>,
-							 <&osc1>, <&cb_intosc_hs_div2_clk>,
-							 <&f2s_free_clk>;
-					reg = <0x60>;
-				};
-
-				noc_free_clk: noc_free_clk {
-					#clock-cells = <0>;
-					compatible = "altr,socfpga-a10-perip-clk";
-					clocks = <&main_noc_base_clk>, <&peri_noc_base_clk>,
-							 <&osc1>, <&cb_intosc_hs_div2_clk>,
-							 <&f2s_free_clk>;
-					reg = <0x64>;
-				};
-
-				s2f_user1_free_clk: s2f_user1_free_clk {
-					#clock-cells = <0>;
-					compatible = "altr,socfpga-a10-perip-clk";
-					clocks = <&main_s2f_usr1_clk>, <&peri_s2f_usr1_clk>,
-							 <&osc1>, <&cb_intosc_hs_div2_clk>,
-							 <&f2s_free_clk>;
-					reg = <0x104>;
-				};
-
-				sdmmc_free_clk: sdmmc_free_clk {
-					#clock-cells = <0>;
-					compatible = "altr,socfpga-a10-perip-clk";
-					clocks = <&main_sdmmc_clk>, <&peri_sdmmc_clk>,
-							 <&osc1>, <&cb_intosc_hs_div2_clk>,
-							 <&f2s_free_clk>;
-					fixed-divider = <4>;
-					reg = <0xF8>;
-				};
-
-				l4_sys_free_clk: l4_sys_free_clk {
-					#clock-cells = <0>;
-					compatible = "altr,socfpga-a10-perip-clk";
-					clocks = <&noc_free_clk>;
-					fixed-divider = <4>;
-				};
-
-				l4_main_clk: l4_main_clk {
-					#clock-cells = <0>;
-					compatible = "altr,socfpga-a10-gate-clk";
-					clocks = <&noc_free_clk>;
-					div-reg = <0xA8 0 2>;
-					clk-gate = <0x48 1>;
-				};
-
-				l4_mp_clk: l4_mp_clk {
-					#clock-cells = <0>;
-					compatible = "altr,socfpga-a10-gate-clk";
-					clocks = <&noc_free_clk>;
-					div-reg = <0xA8 8 2>;
-					clk-gate = <0x48 2>;
-				};
-
-				l4_sp_clk: l4_sp_clk {
-					#clock-cells = <0>;
-					compatible = "altr,socfpga-a10-gate-clk";
-					clocks = <&noc_free_clk>;
-					div-reg = <0xA8 16 2>;
-					clk-gate = <0x48 3>;
-				};
-
-				mpu_periph_clk: mpu_periph_clk {
-					#clock-cells = <0>;
-					compatible = "altr,socfpga-a10-gate-clk";
-					clocks = <&mpu_free_clk>;
-					fixed-divider = <4>;
-					clk-gate = <0x48 0>;
-				};
-
-				sdmmc_clk: sdmmc_clk {
-					#clock-cells = <0>;
-					compatible = "altr,socfpga-a10-gate-clk";
-					clocks = <&sdmmc_free_clk>;
-					clk-gate = <0xC8 5>;
-					clk-phase = <0 135>;
-				};
-
-				qspi_clk: qspi_clk {
-					#clock-cells = <0>;
-					compatible = "altr,socfpga-a10-gate-clk";
-					clocks = <&l4_main_clk>;
-					clk-gate = <0xC8 11>;
-				};
-
-				nand_clk: nand_clk {
-					#clock-cells = <0>;
-					compatible = "altr,socfpga-a10-gate-clk";
-					clocks = <&l4_mp_clk>;
-					clk-gate = <0xC8 10>;
-				};
-
-				spi_m_clk: spi_m_clk {
-					#clock-cells = <0>;
-					compatible = "altr,socfpga-a10-gate-clk";
-					clocks = <&l4_main_clk>;
-					clk-gate = <0xC8 9>;
-				};
-
-				usb_clk: usb_clk {
-					#clock-cells = <0>;
-					compatible = "altr,socfpga-a10-gate-clk";
-					clocks = <&l4_mp_clk>;
-					clk-gate = <0xC8 8>;
-				};
-
-				s2f_usr1_clk: s2f_usr1_clk {
-					#clock-cells = <0>;
-					compatible = "altr,socfpga-a10-gate-clk";
-					clocks = <&peri_s2f_usr1_clk>;
-					clk-gate = <0xC8 6>;
-				};
-			};
+		socfpga_axi_setup: stmmac-axi-config {
+			snps,wr_osr_lmt = <0xf>;
+			snps,rd_osr_lmt = <0xf>;
+			snps,blen = <0 0 0 0 16 0 0>;
 		};
 
 		gmac0: ethernet@ff800000 {
@@ -435,6 +429,7 @@
 			clock-names = "stmmaceth";
 			resets = <&rst EMAC0_RESET>;
 			reset-names = "stmmaceth";
+			snps,axi-config = <&socfpga_axi_setup>;
 			status = "disabled";
 		};
 
@@ -454,6 +449,7 @@
 			clock-names = "stmmaceth";
 			resets = <&rst EMAC1_RESET>;
 			reset-names = "stmmaceth";
+			snps,axi-config = <&socfpga_axi_setup>;
 			status = "disabled";
 		};
 
@@ -471,6 +467,7 @@
 			rx-fifo-depth = <16384>;
 			clocks = <&l4_mp_clk>;
 			clock-names = "stmmaceth";
+			snps,axi-config = <&socfpga_axi_setup>;
 			status = "disabled";
 		};
 
@@ -483,6 +480,7 @@
 
 			porta: gpio-controller@0 {
 				compatible = "snps,dw-apb-gpio-port";
+				bank-name = "porta";
 				gpio-controller;
 				#gpio-cells = <2>;
 				snps,nr-gpios = <29>;
@@ -502,6 +500,7 @@
 
 			portb: gpio-controller@0 {
 				compatible = "snps,dw-apb-gpio-port";
+				bank-name = "portb";
 				gpio-controller;
 				#gpio-cells = <2>;
 				snps,nr-gpios = <29>;
@@ -521,6 +520,7 @@
 
 			portc: gpio-controller@0 {
 				compatible = "snps,dw-apb-gpio-port";
+				bank-name = "portc";
 				gpio-controller;
 				#gpio-cells = <2>;
 				snps,nr-gpios = <27>;
@@ -590,37 +590,24 @@
 			status = "disabled";
 		};
 
-		sdr: sdr@0xffcfb100 {
-			compatible = "syscon";
-			reg = <0xffcfb100 0x80>;
-		};
-
-		spi0: spi@ffda4000 {
+		spi1: spi@ffda5000 {
 			compatible = "snps,dw-apb-ssi";
 			#address-cells = <1>;
 			#size-cells = <0>;
-			reg = <0xffda4000 0x100>;
-			interrupts = <0 101 IRQ_TYPE_LEVEL_HIGH>;
+			reg = <0xffda5000 0x100>;
+			interrupts = <0 102 4>;
 			num-chipselect = <4>;
 			bus-num = <0>;
+			/*32bit_access;*/
 			tx-dma-channel = <&pdma 16>;
 			rx-dma-channel = <&pdma 17>;
 			clocks = <&spi_m_clk>;
 			status = "disabled";
 		};
 
-		spi1: spi@ffda5000 {
-			compatible = "snps,dw-apb-ssi";
-			#address-cells = <1>;
-			#size-cells = <0>;
-			reg = <0xffda5000 0x100>;
-			interrupts = <0 102 IRQ_TYPE_LEVEL_HIGH>;
-			num-chipselect = <4>;
-			bus-num = <0>;
-			tx-dma-channel = <&pdma 20>;
-			rx-dma-channel = <&pdma 21>;
-			clocks = <&spi_m_clk>;
-			status = "disabled";
+		sdr: sdr@ffc25000 {
+			compatible = "altr,sdr-ctl", "syscon";
+			reg = <0xffcfb100 0x80>;
 		};
 
 		L2: l2-cache@fffff000 {
@@ -629,6 +616,9 @@
 			interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>;
 			cache-unified;
 			cache-level = <2>;
+			prefetch-data = <1>;
+			prefetch-instr = <1>;
+			arm,shared-override;
 		};
 
 		mmc: dwmmc0@ff808000 {
@@ -638,18 +628,30 @@
 			reg = <0xff808000 0x1000>;
 			interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>;
 			fifo-depth = <0x400>;
-			bus-width = <4>;
 			clocks = <&l4_mp_clk>, <&sdmmc_clk>;
 			clock-names = "biu", "ciu";
 			status = "disabled";
 		};
 
+		nand: nand@ffb90000 {
+			#address-cells = <1>;
+			#size-cells = <1>;
+			compatible = "denali,denali-nand-dt", "altr,socfpga-denali-nand";
+			reg = <0xffb90000 0x72000>,
+			      <0xffb80000 0x10000>;
+			reg-names = "nand_data", "denali_reg";
+			interrupts = <0 99 4>;
+			dma-mask = <0xffffffff>;
+			clocks = <&nand_clk>;
+			status = "disabled";
+		};
+
 		ocram: sram@ffe00000 {
 			compatible = "mmio-sram";
 			reg = <0xffe00000 0x40000>;
 		};
 
-		eccmgr: eccmgr@ffd06000 {
+		eccmgr: eccmgr {
 			compatible = "altr,socfpga-a10-ecc-manager";
 			altr,sysmgr-syscon = <&sysmgr>;
 			#address-cells = <1>;
@@ -681,16 +683,6 @@
 					     <33 IRQ_TYPE_LEVEL_HIGH>;
 			};
 
-			sdmmca-ecc@ff8c2c00 {
-				compatible = "altr,socfpga-sdmmc-ecc";
-				reg = <0xff8c2c00 0x400>;
-				altr,ecc-parent = <&mmc>;
-				interrupts = <15 IRQ_TYPE_LEVEL_HIGH>,
-					<47 IRQ_TYPE_LEVEL_HIGH>,
-					<16 IRQ_TYPE_LEVEL_HIGH>,
-					<48 IRQ_TYPE_LEVEL_HIGH>;
-			};
-
 			emac0-rx-ecc@ff8c0800 {
 				compatible = "altr,socfpga-eth-mac-ecc";
 				reg = <0xff8c0800 0x400>;
@@ -724,19 +716,17 @@
 			};
 		};
 
-		qspi: qspi@ff809000 {
+		qspi: spi@ff809000 {
+			compatible = "cdns,qspi-nor", "cadence,qspi";
 			#address-cells = <1>;
 			#size-cells = <0>;
-			compatible = "cadence,qspi";
 			reg = <0xff809000 0x100>,
-				<0xffa00000 0x100000>;
+			      <0xffa00000 0x100000>;
 			interrupts = <0 100 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&l4_main_clk>;
-			ext-decoder = <0>;  /* external decoder */
-			num-chipselect = <4>;
 			cdns,fifo-depth = <128>;
 			cdns,fifo-width = <4>;
-			bus-num = <2>;
+			cdns,trigger-address = <0x00000000>;
+			clocks = <&qspi_clk>;
 			status = "disabled";
 		};
 
@@ -818,7 +808,7 @@
 			status = "disabled";
 		};
 
-		usbphy0: usbphy@0 {
+		usbphy0: usbphy {
 			#phy-cells = <0>;
 			compatible = "usb-nop-xceiv";
 			status = "okay";