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authorSimon Goldschmidt <simon.k.r.goldschmidt@gmail.com>2018-11-02 11:54:52 +0100
committerMarek Vasut <marex@denx.de>2018-11-29 12:45:15 +0100
commitc402e8170245a0ca2b9398185638b349eeff10a3 (patch)
tree27e414029b8c7541c113998e32fc83c0bcefb563 /arch/arm/dts/socfpga_cyclone5_socdk-u-boot.dtsi
parent2a3a99932b8ce12fefd65bde03dc4a33b5317b45 (diff)
dts: arm: socfpga: merge gen5 devicetrees from linux
Add -u-boot.dtsi files to keep the current U-Boot behaviour: - add u-boot,dm-pre-reloc where required - disable watchdog - set uart clock frequency - add gpio bank-name properties where appropriate: - make qspi work (add alias for spi0, fix compatible for flash) - enable usb (status okay, add alias for udc0) Adapt board dts files that are not in Linux to keep their old behaviour. Change licenses to SPDX. (Patman warnings/errors are in 1:1 copied files from Linux) Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Diffstat (limited to 'arch/arm/dts/socfpga_cyclone5_socdk-u-boot.dtsi')
-rw-r--r--arch/arm/dts/socfpga_cyclone5_socdk-u-boot.dtsi72
1 files changed, 72 insertions, 0 deletions
diff --git a/arch/arm/dts/socfpga_cyclone5_socdk-u-boot.dtsi b/arch/arm/dts/socfpga_cyclone5_socdk-u-boot.dtsi
new file mode 100644
index 0000000000..9436e0fa8b
--- /dev/null
+++ b/arch/arm/dts/socfpga_cyclone5_socdk-u-boot.dtsi
@@ -0,0 +1,72 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * U-Boot additions
+ *
+ * Copyright (C) 2012 Altera Corporation <www.altera.com>
+ * Copyright (c) 2018 Simon Goldschmidt
+ */
+
+/{
+ aliases {
+ spi0 = "/soc/spi@ff705000";
+ udc0 = &usb1;
+ };
+
+ soc {
+ u-boot,dm-pre-reloc;
+ };
+};
+
+&can0 {
+ status = "okay";
+};
+
+&watchdog0 {
+ status = "disabled";
+};
+
+&mmc {
+ u-boot,dm-pre-reloc;
+};
+
+&qspi {
+ u-boot,dm-pre-reloc;
+};
+
+&flash0 {
+ compatible = "n25q00", "spi-flash";
+ u-boot,dm-pre-reloc;
+
+ partition@qspi-boot {
+ /* 8MB for raw data. */
+ label = "Flash 0 Raw Data";
+ reg = <0x0 0x800000>;
+ };
+
+ partition@qspi-rootfs {
+ /* 120MB for jffs2 data. */
+ label = "Flash 0 jffs2 Filesystem";
+ reg = <0x800000 0x7800000>;
+ };
+};
+
+&uart0 {
+ clock-frequency = <100000000>;
+ u-boot,dm-pre-reloc;
+};
+
+&uart1 {
+ clock-frequency = <100000000>;
+};
+
+&porta {
+ bank-name = "porta";
+};
+
+&portb {
+ bank-name = "portb";
+};
+
+&portc {
+ bank-name = "portc";
+};