diff options
| author | Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> | 2019-03-01 20:12:29 +0100 |
|---|---|---|
| committer | Marek Vasut <marex@denx.de> | 2019-04-17 22:20:16 +0200 |
| commit | 7357c2cbc0b4c4c0cf2d6fa1253cda6f77cf06da (patch) | |
| tree | 6bd5fd12d895041604fe3376c28c727644cef55a /arch/arm/dts/socfpga_cyclone5_sr1500.dts | |
| parent | 42a37d977403d1632bf528013d45c9e6fd5c679c (diff) | |
arm: socfpga: gen5: add reset & sdr node to SPL devicetrees
The SPL for socfpga gen5 currently takes all peripherals out of reset
unconditionally. To implement proper reset handling for peripherals,
the reset node has to be provided with the SPL dts.
In preparation to move the DDR driver to DM, the sdr node is required
in SPL, too.
This patch adds "u-boot,dm-pre-reloc" to U-Boot specific dtsi addon
files so that the reset manager and SDR driver correctly probe in SPL.
It centralizes these settings into a common file since in contrast to
boot-type specific nodes, "soc", "rst" and "sdr" are always needed.
Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Diffstat (limited to 'arch/arm/dts/socfpga_cyclone5_sr1500.dts')
| -rw-r--r-- | arch/arm/dts/socfpga_cyclone5_sr1500.dts | 5 |
1 files changed, 1 insertions, 4 deletions
diff --git a/arch/arm/dts/socfpga_cyclone5_sr1500.dts b/arch/arm/dts/socfpga_cyclone5_sr1500.dts index 1a18c4f3ba..bb29da6d6c 100644 --- a/arch/arm/dts/socfpga_cyclone5_sr1500.dts +++ b/arch/arm/dts/socfpga_cyclone5_sr1500.dts @@ -4,6 +4,7 @@ */ #include "socfpga_cyclone5.dtsi" +#include "socfpga-common-u-boot.dtsi" / { model = "SoCFPGA Cyclone V SR1500"; @@ -27,10 +28,6 @@ device_type = "memory"; reg = <0x0 0x40000000>; /* 1GB */ }; - - soc { - u-boot,dm-pre-reloc; - }; }; &gmac1 { |