diff options
| author | Vikas Manocha <vikas.manocha@st.com> | 2017-04-10 15:03:03 -0700 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2017-05-08 11:57:22 -0400 |
| commit | bfea69ad27936d619c0eb3c1be55cc292df8d7f5 (patch) | |
| tree | 14e38035d8f8d84ec50fc92a62536ced09a40e92 /arch/arm/dts/stm32f746-disco.dts | |
| parent | a241c241cf2b08bb7905f4825e76e49944648b60 (diff) | |
stm32f7: sdram: correct sdram configuration as per micron sdram
Actually the sdram memory on stm32f746 discovery board is micron part
MT48LC_4M32_B2B5_6A. This patch does the modification required in the
device tree node & driver for the same.
Also we are passing here all the timing parameters in terms of clock
cycles, so no need to convert time(ns or ms) to cycles.
Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
cc: Christophe KERELLO <christophe.kerello@st.com>
Diffstat (limited to 'arch/arm/dts/stm32f746-disco.dts')
| -rw-r--r-- | arch/arm/dts/stm32f746-disco.dts | 13 |
1 files changed, 8 insertions, 5 deletions
diff --git a/arch/arm/dts/stm32f746-disco.dts b/arch/arm/dts/stm32f746-disco.dts index 8e4576bdc1..e720ff1207 100644 --- a/arch/arm/dts/stm32f746-disco.dts +++ b/arch/arm/dts/stm32f746-disco.dts @@ -106,12 +106,15 @@ status = "okay"; mr-nbanks = <1>; - /* sdram memory configuration from sdram datasheet IS42S16400J */ + /* Memory configuration from sdram datasheet MT48LC_4M32_B2B5-6A */ bank1: bank@0 { - st,sdram-control = /bits/ 8 <NO_COL_8 NO_ROW_12 MWIDTH_16 BANKS_2 - CAS_3 RD_BURST_EN RD_PIPE_DL_0>; - st,sdram-timing = /bits/ 8 <TMRD_1 TXSR_60 TRAS_42 TRC_60 TRP_18 - TRCD_18>; + st,sdram-control = /bits/ 8 <NO_COL_8 NO_ROW_12 MWIDTH_16 BANKS_4 + CAS_3 SDCLK_2 RD_BURST_EN + RD_PIPE_DL_0>; + st,sdram-timing = /bits/ 8 <TMRD_2 TXSR_6 TRAS_4 TRC_6 TWR_2 + TRP_2 TRCD_2>; + /* refcount = (64msec/total_row_sdram)*freq - 20 */ + st,sdram-refcount = < 1542 >; }; }; |