diff options
| author | Patrice Chotard <patrice.chotard@st.com> | 2018-08-10 17:12:11 +0200 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2018-09-25 21:47:39 -0400 |
| commit | 8e9c94d7663510cbf31cb1d1a30b73f220ccb171 (patch) | |
| tree | 0754501640fc10766c2b70e7ea7220dab4ab6ecd /arch/arm/dts/stm32mp157c.dtsi | |
| parent | 284b27cf81da10d55070a49ee8b739f71377a4fb (diff) | |
ARM: dts: stm32mp1: Add usb gadget support for stm32mp157c-ev1 board
Add DT nodes to enable DWC2 gadget support
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Diffstat (limited to 'arch/arm/dts/stm32mp157c.dtsi')
| -rw-r--r-- | arch/arm/dts/stm32mp157c.dtsi | 36 |
1 files changed, 36 insertions, 0 deletions
diff --git a/arch/arm/dts/stm32mp157c.dtsi b/arch/arm/dts/stm32mp157c.dtsi index cdf2946968..33c5981869 100644 --- a/arch/arm/dts/stm32mp157c.dtsi +++ b/arch/arm/dts/stm32mp157c.dtsi @@ -106,6 +106,26 @@ }; }; + pm_domain { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32mp157c-pd"; + + pd_core_ret: core-ret-power-domain@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + #power-domain-cells = <0>; + label = "CORE-RETENTION"; + + pd_core: core-power-domain@2 { + reg = <2>; + #power-domain-cells = <0>; + label = "CORE"; + }; + }; + }; + soc { compatible = "simple-bus"; #address-cells = <1>; @@ -654,6 +674,22 @@ status = "disabled"; }; + usbotg_hs: usb-otg@49000000 { + compatible = "st,stm32mp1-hsotg", "snps,dwc2"; + reg = <0x49000000 0x10000>; + clocks = <&rcc USBO_K>; + clock-names = "otg"; + resets = <&rcc USBO_R>; + reset-names = "dwc2"; + interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; + g-rx-fifo-size = <256>; + g-np-tx-fifo-size = <32>; + g-tx-fifo-size = <128 128 64 64 64 64 32 32>; + dr_mode = "otg"; + power-domains = <&pd_core>; + status = "disabled"; + }; + rcc: rcc@50000000 { compatible = "st,stm32mp1-rcc", "syscon"; reg = <0x50000000 0x1000>; |