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authorAntonio Borneo <antonio.borneo@st.com>2020-01-28 10:11:01 +0100
committerPatrick Delaunay <patrick.delaunay@st.com>2020-02-13 17:26:22 +0100
commitdb0cd2d3bcd513d8413a8fa0d721c0dc457a9359 (patch)
tree56c1bcba748767d7d29b60b5f82d481abf9d6730 /arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi
parentd35a5af321f33e6bd5b643e1b0356fc2bfa0ba0b (diff)
ARM: dts: stm32mp1: move FDCAN to PLL4_R
LTDC modifies the clock frequency to adapt it to the display. Such frequency change is not detected by the FDCAN driver that instead cache the value at probe and pretend to use it later. Keep the LTDC alone on PLL4_Q by moving the FDCAN to PLL4_R. Signed-off-by: Antonio Borneo <antonio.borneo@st.com> Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Diffstat (limited to 'arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi')
-rw-r--r--arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi b/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi
index 320912edd8..21aa4bfb86 100644
--- a/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi
+++ b/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi
@@ -142,7 +142,7 @@
CLK_UART6_HSI
CLK_UART78_HSI
CLK_SPDIF_PLL4P
- CLK_FDCAN_PLL4Q
+ CLK_FDCAN_PLL4R
CLK_SAI1_PLL3Q
CLK_SAI2_PLL3Q
CLK_SAI3_PLL3Q