diff options
author | Usama Arif <usama.arif@arm.com> | 2020-08-12 16:12:53 +0100 |
---|---|---|
committer | Tom Rini <trini@konsulko.com> | 2020-08-24 14:11:31 -0400 |
commit | 565add124de00c994652a0d2d6d1eb6b2a7c9553 (patch) | |
tree | 5c89010de62d46784c979d8cb79b49d3548a655d /arch/arm/dts/total_compute.dts | |
parent | e61b41517d2a91080f6416fdfb46efab9e5a55b4 (diff) |
board: armltd: Add support for Total Compute platform
Total Compute is based on ARM architecture and has
the following features enabled in u-boot:
- PL011 UART
- PL180 MMC
- NOR Flash
- FIT image with Signature
- AVB
Signed-off-by: Usama Arif <usama.arif@arm.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Diffstat (limited to 'arch/arm/dts/total_compute.dts')
-rw-r--r-- | arch/arm/dts/total_compute.dts | 48 |
1 files changed, 48 insertions, 0 deletions
diff --git a/arch/arm/dts/total_compute.dts b/arch/arm/dts/total_compute.dts new file mode 100644 index 0000000000..4399269a44 --- /dev/null +++ b/arch/arm/dts/total_compute.dts @@ -0,0 +1,48 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2020 Arm Limited + */ + +/dts-v1/; + +/ { + model = "total_compute"; + compatible = "arm,total_compute"; + #address-cells = <2>; + #size-cells = <2>; + + sysreg: sysreg@1c010000 { + compatible = "arm,vexpress-sysreg"; + reg = <0x0 0x001c010000 0x0 0x1000>; + gpio-controller; + #gpio-cells = <2>; + }; + + fixed_3v3: v2m-3v3 { + compatible = "regulator-fixed"; + regulator-name = "3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + mmci@1c050000 { + compatible = "arm,pl180", "arm,primecell"; + reg = <0x0 0x001c050000 0x0 0x1000>; + cd-gpios = <&sysreg 0 0>; + arm,primecell-periphid = <0x00880180>; + wp-gpios = <&sysreg 1 0>; + bus-width = <8>; + max-frequency = <12000000>; + vmmc-supply = <&fixed_3v3>; + clocks = <&clock24mhz>, <&clock24mhz>; + clock-names = "mclk", "apb_pclk"; + }; + + clock24mhz: clock24mhz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + clock-output-names = "bp:clock24mhz"; + }; +}; |