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| author | Masahiro Yamada <yamada.masahiro@socionext.com> | 2018-12-19 20:03:20 +0900 |
|---|---|---|
| committer | Masahiro Yamada <yamada.masahiro@socionext.com> | 2018-12-29 11:38:38 +0900 |
| commit | 94bf34b17277c77d42ae9137262adf55143b0d48 (patch) | |
| tree | 6aa03fa40583e3abbfc9a0accfca1b5c4a016b0a /arch/arm/dts/uniphier-ld20-ref.dts | |
| parent | 9d43649a7740cf715c750929d19661a35144e7d1 (diff) | |
clk: uniphier: add NAND 200MHz clock
The Denali NAND controller IP needs three clocks:
- clk: controller core clock
- clk_x: bus interface clock
- ecc_clk: clock at which ECC circuitry is run
Currently, only the first one (50MHz) is provided. The rest of the
two clock ports must be connected to the 200MHz clock line. Add this.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Diffstat (limited to 'arch/arm/dts/uniphier-ld20-ref.dts')
0 files changed, 0 insertions, 0 deletions