diff options
| author | Tom Rini <trini@konsulko.com> | 2018-04-09 11:06:21 -0400 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2018-04-09 11:06:21 -0400 |
| commit | 2600df4f8ef12ece9cec13030005919e0ba2b0d5 (patch) | |
| tree | 993f32ce9c39fadc2effffb3690dc60cd1add303 /arch/arm/dts/zynqmp-clk.dtsi | |
| parent | 844fb498cc978608ec88bdf29913c0d46c85bfff (diff) | |
| parent | f190eaf002bf1434587d57c726b3dabfabbc8074 (diff) | |
Merge tag 'xilinx-for-v2018.05-rc2' of git://git.denx.de/u-boot-microblaze
Xilinx changes for v2018.05-rc2
- Various DT changes and sync with mainline kernel
- Various defconfig updates
- Add SPL init for zcu102 revA
- Add new zynqmp boards zcu100/zcu104/zcu106/zcu111/zc12XX
and zc1751-dc3
- Net fixes - xlnx,phy-type
- 64bit axi ethernet support
- arasan: Fix nand write issue
- fpga fixes
- Maintainer file updates
Diffstat (limited to 'arch/arm/dts/zynqmp-clk.dtsi')
| -rw-r--r-- | arch/arm/dts/zynqmp-clk.dtsi | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/arch/arm/dts/zynqmp-clk.dtsi b/arch/arm/dts/zynqmp-clk.dtsi index f6e83e1513..a8664e8187 100644 --- a/arch/arm/dts/zynqmp-clk.dtsi +++ b/arch/arm/dts/zynqmp-clk.dtsi @@ -1,11 +1,10 @@ +// SPDX-License-Identifier: GPL-2.0+ /* * Clock specification for Xilinx ZynqMP * - * (C) Copyright 2015, Xilinx, Inc. + * (C) Copyright 2015 - 2018, Xilinx, Inc. * * Michal Simek <michal.simek@xilinx.com> - * - * SPDX-License-Identifier: GPL-2.0+ */ / { @@ -26,6 +25,7 @@ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <200000000>; + u-boot,dm-pre-reloc; }; clk250: clk250 { |