diff options
| author | Tom Rini <trini@konsulko.com> | 2020-04-30 11:31:33 -0400 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2020-04-30 11:34:01 -0400 |
| commit | 6d7dacf726ca043a3f5487549bbfa506c990c813 (patch) | |
| tree | 0976c82eca83479ba9337f9a1824572ea0b9578e /arch/arm/dts/zynqmp-e-a2197-00-revA.dts | |
| parent | b9da77f1958aab4ec50ff2f095b40464ca2489dd (diff) | |
| parent | 27d706937a5c72f0414a540ca20fd36b4b72bda7 (diff) | |
Merge tag 'xilinx-for-v2020.07-rc2' of https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze
Xilinx changes for v2020.07-rc2
mmc:
- Fix dt property handling via generic function
clk:
- Fix versal watchdog clock setting
nand:
- Fix zynq nand command comparison
xilinx:
- Enable ubifs
- Sync board_late_init configurations with initrd_high setup
- Make custom distro boot more verbose
zynq:
- Kconfig alignments
- Fix nand cse configuration
zynqmp:
- Fix zcu104 low level qspi configuration
- Small DT updates
Signed-off-by: Tom Rini <trini@konsulko.com>
Diffstat (limited to 'arch/arm/dts/zynqmp-e-a2197-00-revA.dts')
| -rw-r--r-- | arch/arm/dts/zynqmp-e-a2197-00-revA.dts | 22 |
1 files changed, 16 insertions, 6 deletions
diff --git a/arch/arm/dts/zynqmp-e-a2197-00-revA.dts b/arch/arm/dts/zynqmp-e-a2197-00-revA.dts index 39b5d7fff9..bf982e2218 100644 --- a/arch/arm/dts/zynqmp-e-a2197-00-revA.dts +++ b/arch/arm/dts/zynqmp-e-a2197-00-revA.dts @@ -162,9 +162,9 @@ "", "", "", "", "", /* 65 - 69 */ "", "", "", "", "", /* 70 - 74 */ "", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */ - "", "", /* 78 - 79 */ - "", "", "", "", "", /* 80 - 84 */ - "", "", "", "", "", /* 85 -89 */ + "SYSCTLR_VERSAL_MODE0", "SYSCTLR_VERSAL_MODE1", /* 78 - 79 */ + "SYSCTLR_VERSAL_MODE2", "SYSCTLR_VERSAL_MODE3", "SYSCTLR_POR_B_LS", "", "", /* 80 - 84 */ + "", "", "", "", "", /* 85 - 89 */ "", "", "", "", "", /* 90 - 94 */ "", "", "", "", "", /* 95 - 99 */ "", "", "", "", "", /* 100 - 104 */ @@ -198,9 +198,6 @@ #size-cells = <0>; reg = <0>; /* u152 IR35215 0x16/0x46 vcc_soc */ - /* u160 IRPS5401 0x17/0x47 */ - /* u167 IRPS5401 0x1c/0x4c */ - /* u175 IRPS5401 0x1d/0x4d */ /* u179 ir38164 0x19/0x49 vcco_500 */ /* u181 ir38164 0x1a/0x4a vcco_501 */ /* u183 ir38164 0x1b/0x4b vcco_502 */ @@ -209,6 +206,19 @@ /* u189 ir38164 0x20/0x50 mgtyavtt */ /* u194 ir38164 0x13/0x43 vdd1_1v8_lp4 */ /* u195 ir38164 0x14/0x44 vdd2_1v8_lp4 */ + + irps5401_47: irps5401@47 { /* IRPS5401 - u160 */ + compatible = "infineon,irps5401"; + reg = <0x47>; /* pmbus / i2c 0x17 */ + }; + irps5401_4c: irps5401@4c { /* IRPS5401 - u167 */ + compatible = "infineon,irps5401"; + reg = <0x4c>; /* pmbus / i2c 0x1c */ + }; + irps5401_4d: irps5401@4d { /* IRPS5401 - u175 */ + compatible = "infineon,irps5401"; + reg = <0x4d>; /* pmbus / i2c 0x1d */ + }; }; i2c@1 { /* PMBUS1_INA226 */ #address-cells = <1>; |