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authorSaeed Nowshadi <saeed.nowshadi@xilinx.com>2020-03-27 08:12:20 -0700
committerMichal Simek <michal.simek@xilinx.com>2020-04-27 13:57:18 +0200
commit783814288b28cc6d63117c15b5755f6396f0c799 (patch)
treede48e79653e948bc17d7625b8715c80ebad1c7fd /arch/arm/dts/zynqmp-e-a2197-00-revA.dts
parent7eab624baf96a6d967416ffeb51e3fef289c47ae (diff)
arm64: zynqmp: Add label to GPIO lines for boot mode and POR
Add label to GPIO lines controlling boot mode and POR EMIO pins so System Controller can assert those lines on Versal. Signed-off-by: Saeed Nowshadi <saeed.nowshadi@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Diffstat (limited to 'arch/arm/dts/zynqmp-e-a2197-00-revA.dts')
-rw-r--r--arch/arm/dts/zynqmp-e-a2197-00-revA.dts6
1 files changed, 3 insertions, 3 deletions
diff --git a/arch/arm/dts/zynqmp-e-a2197-00-revA.dts b/arch/arm/dts/zynqmp-e-a2197-00-revA.dts
index 39b5d7fff9..65cf591494 100644
--- a/arch/arm/dts/zynqmp-e-a2197-00-revA.dts
+++ b/arch/arm/dts/zynqmp-e-a2197-00-revA.dts
@@ -162,9 +162,9 @@
"", "", "", "", "", /* 65 - 69 */
"", "", "", "", "", /* 70 - 74 */
"", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */
- "", "", /* 78 - 79 */
- "", "", "", "", "", /* 80 - 84 */
- "", "", "", "", "", /* 85 -89 */
+ "SYSCTLR_VERSAL_MODE0", "SYSCTLR_VERSAL_MODE1", /* 78 - 79 */
+ "SYSCTLR_VERSAL_MODE2", "SYSCTLR_VERSAL_MODE3", "SYSCTLR_POR_B_LS", "", "", /* 80 - 84 */
+ "", "", "", "", "", /* 85 - 89 */
"", "", "", "", "", /* 90 - 94 */
"", "", "", "", "", /* 95 - 99 */
"", "", "", "", "", /* 100 - 104 */