Merge tag 'xilinx-for-v2018.05-rc2' of git://git.denx.de/u-boot-microblaze

Xilinx changes for v2018.05-rc2

- Various DT changes and sync with mainline kernel
- Various defconfig updates
- Add SPL init for zcu102 revA
- Add new zynqmp boards zcu100/zcu104/zcu106/zcu111/zc12XX
  and zc1751-dc3
- Net fixes - xlnx,phy-type
- 64bit axi ethernet support
- arasan: Fix nand write issue
- fpga fixes
- Maintainer file updates

1 files changed, 7 insertions, 8 deletions

diff --git a/arch/arm/dts/zynqmp-zcu102-rev1.0.dts b/arch/arm/dts/zynqmp-zcu102-rev1.0.dts
index 323a674e3a..6647e97edb 100644
--- a/arch/arm/dts/zynqmp-zcu102-rev1.0.dts
+++ b/arch/arm/dts/zynqmp-zcu102-rev1.0.dts
@@ -1,11 +1,10 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * dts file for Xilinx ZynqMP ZCU102 Rev1.0
  *
- * (C) Copyright 2016, Xilinx, Inc.
+ * (C) Copyright 2016 - 2018, Xilinx, Inc.
  *
  * Michal Simek <michal.simek@xilinx.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
  */
 
 #include "zynqmp-zcu102-revB.dts"
@@ -15,23 +14,23 @@
 	compatible = "xlnx,zynqmp-zcu102-rev1.0", "xlnx,zynqmp-zcu102", "xlnx,zynqmp";
 };
 
-&eeprom  {
+&eeprom {
 	#address-cells = <1>;
 	#size-cells = <1>;
 
-	board_sn: board_sn@0 {
+	board_sn: board-sn@0 {
 		reg = <0x0 0x14>;
 	};
 
-	eth_mac: eth_mac@20 {
+	eth_mac: eth-mac@20 {
 		reg = <0x20 0x6>;
 	};
 
-	board_name: board_name@d0 {
+	board_name: board-name@d0 {
 		reg = <0xd0 0x6>;
 	};
 
-	board_revision: board_revision@e0 {
+	board_revision: board-revision@e0 {
 		reg = <0xe0 0x3>;
 	};
 };