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| author | Masahiro Yamada <yamada.masahiro@socionext.com> | 2016-02-05 13:21:07 +0900 |
|---|---|---|
| committer | Masahiro Yamada <yamada.masahiro@socionext.com> | 2016-02-14 17:07:46 +0900 |
| commit | f775c09d00cc355a87cf4ba935eff86eacd0c961 (patch) | |
| tree | 03b12c19637a6bbc0f808e77a3806402db3f24b9 /arch/arm/dts/zynqmp.dtsi | |
| parent | c9552895a8055fed424d6817008fccd37dbfd01c (diff) | |
ARM: uniphier: adjust DDR clock delay line for ProXstream2
It turned out that DDR channel 2 was not working on ProXstream2
Vodka board. Add the missing ACBLDR0 register setting to adjust
the delay between the clock lines and the address/command lines.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Diffstat (limited to 'arch/arm/dts/zynqmp.dtsi')
0 files changed, 0 insertions, 0 deletions