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authorMichal Simek <michal.simek@xilinx.com>2017-02-14 17:40:21 +0100
committerMichal Simek <michal.simek@xilinx.com>2017-08-02 09:11:51 +0200
commit0b180d02a30191478ec8088661049e19930253f7 (patch)
treef43f64b13e373fef33bf6558be02171fb27c31e8 /arch/arm/dts
parent6364a5d4bd55beeedc11171419acd0bdff17a599 (diff)
arm: zynq: Label whole PL part as fpga_full region
This will simplify dt overlay structure for the whole PL. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Moritz Fischer <moritz.fischer@ettus.com>
Diffstat (limited to 'arch/arm/dts')
-rw-r--r--arch/arm/dts/zynq-7000.dtsi8
1 files changed, 8 insertions, 0 deletions
diff --git a/arch/arm/dts/zynq-7000.dtsi b/arch/arm/dts/zynq-7000.dtsi
index 34fc6e5f89..f993e19ef2 100644
--- a/arch/arm/dts/zynq-7000.dtsi
+++ b/arch/arm/dts/zynq-7000.dtsi
@@ -38,6 +38,14 @@
};
};
+ fpga_full: fpga-full {
+ compatible = "fpga-region";
+ fpga-mgr = <&devcfg>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ };
+
pmu@f8891000 {
compatible = "arm,cortex-a9-pmu";
interrupts = <0 5 4>, <0 6 4>;