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authorVignesh Raghavendra <vigneshr@ti.com>2019-10-23 13:30:02 +0530
committerStefan Roese <sr@denx.de>2019-10-24 09:49:16 +0200
commit358032f9a5d76ecf64a52ad5fa189246fd82f834 (patch)
tree4728fb99f847c4d10f6c72f4df130be324098588 /arch/arm/dts
parentc2dfd0a4d81faeb50aa0cfe36bf1835a40811304 (diff)
arm: dts: k3-j721e-mcu-wakeup: Add HyperBus Controller node
Add DT node for HyperBus Memory Controller in the FSS. On J721e, its not possible to use OSPI0 and HBMC simultaneously as they are muxed within the Flash Subsystem hence disable HBMC by default as keep OSPI enabled. Bootloader will fixup DT when it detects HyperFlash instead of OSPI. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'arch/arm/dts')
-rw-r--r--arch/arm/dts/k3-j721e-mcu-wakeup.dtsi26
1 files changed, 26 insertions, 0 deletions
diff --git a/arch/arm/dts/k3-j721e-mcu-wakeup.dtsi b/arch/arm/dts/k3-j721e-mcu-wakeup.dtsi
index b958b5b3c1..92beeea34d 100644
--- a/arch/arm/dts/k3-j721e-mcu-wakeup.dtsi
+++ b/arch/arm/dts/k3-j721e-mcu-wakeup.dtsi
@@ -107,4 +107,30 @@
loczrama = <1>;
};
};
+
+ fss: fss@47000000 {
+ compatible = "syscon", "simple-mfd";
+ reg = <0x0 0x47000000 0x0 0x100>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ hbmc_mux: hbmc-mux {
+ compatible = "mmio-mux";
+ #mux-control-cells = <1>;
+ mux-reg-masks = <0x4 0x2>; /* HBMC select */
+ };
+
+ hbmc: hyperbus@47034000 {
+ compatible = "ti,j721e-hbmc", "ti,am654-hbmc";
+ reg = <0x0 0x47034000 0x0 0x100>,
+ <0x5 0x00000000 0x1 0x0000000>;
+ power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>;
+ #address-cells = <2>;
+ #size-cells = <1>;
+ mux-controls = <&hbmc_mux 0>;
+ assigned-clocks = <&k3_clks 102 0>;
+ assigned-clock-rates = <250000000>;
+ };
+ };
};