Merge branch '2020-07-28-misc-soc-improvements'

- Assorted MediaTek improvements
- s5p4418 support
- QEMU ARM platform improvements
- Qualcomm IPQ40xx support

7 files changed, 717 insertions, 6 deletions

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index f01eb7bf5f..caa7756c5d 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -147,6 +147,9 @@ dtb-$(CONFIG_ROCKCHIP_RV1108) += \
 	rv1108-elgin-r1.dtb \
 	rv1108-evb.dtb
 
+dtb-$(CONFIG_ARCH_S5P4418) += \
+	s5p4418-nanopi2.dtb
+
 dtb-$(CONFIG_ARCH_MESON) += \
 	meson-gxbb-nanopi-k2.dtb \
 	meson-gxbb-odroidc2.dtb \
@@ -946,6 +949,7 @@ dtb-$(CONFIG_SOC_K3_J721E) += k3-j721e-common-proc-board.dtb \
 
 dtb-$(CONFIG_ARCH_MEDIATEK) += \
 	mt7622-rfb.dtb \
+	mt7623a-unielec-u7623-02-emmc.dtb \
 	mt7623n-bananapi-bpi-r2.dtb \
 	mt7629-rfb.dtb \
 	mt8512-bm1-emmc.dtb \
diff --git a/arch/arm/dts/mt7623a-unielec-u7623-02-emmc.dts b/arch/arm/dts/mt7623a-unielec-u7623-02-emmc.dts
new file mode 100644
index 0000000000..fdeec75b05
--- /dev/null
+++ b/arch/arm/dts/mt7623a-unielec-u7623-02-emmc.dts
@@ -0,0 +1,211 @@
+/*
+ * Copyright (C) 2018 MediaTek Inc.
+ * Author: Ryder Lee <ryder.lee@mediatek.com>
+ *
+ * SPDX-License-Identifier: (GPL-2.0 OR MIT)
+ */
+
+/dts-v1/;
+#include "mt7623.dtsi"
+#include "mt7623-u-boot.dtsi"
+
+/ {
+	model = "UniElec U7623-02 eMMC";
+	compatible = "unielec,u7623-02-emmc", "mediatek,mt7623";
+
+	memory@80000000 {
+		device_type = "memory";
+		reg = <0 0x80000000 0 0x20000000>;
+	};
+
+	chosen {
+		stdout-path = &uart2;
+		tick-timer = &timer0;
+	};
+
+	reg_1p8v: regulator-1p8v {
+		compatible = "regulator-fixed";
+		regulator-name = "fixed-1.8V";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		regulator-boot-on;
+		regulator-always-on;
+	};
+
+	reg_3p3v: regulator-3p3v {
+		compatible = "regulator-fixed";
+		regulator-name = "fixed-3.3V";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-boot-on;
+		regulator-always-on;
+	};
+
+	reg_5v: regulator-5v {
+		compatible = "regulator-fixed";
+		regulator-name = "fixed-5V";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		regulator-boot-on;
+		regulator-always-on;
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		led3 {
+			label = "u7623-01:green:led3";
+			gpios = <&gpio 14 GPIO_ACTIVE_LOW>;
+			default-state = "off";
+		};
+
+		led4 {
+			label = "u7623-01:green:led4";
+			gpios = <&gpio 15 GPIO_ACTIVE_LOW>;
+			default-state = "off";
+		};
+	};
+};
+
+&eth {
+	status = "okay";
+	mediatek,gmac-id = <0>;
+	phy-mode = "rgmii";
+	mediatek,switch = "mt7530";
+	mediatek,mcm;
+
+	fixed-link {
+		speed = <1000>;
+		full-duplex;
+	};
+};
+
+&mmc0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&mmc0_pins_default>;
+	status = "okay";
+	bus-width = <8>;
+	max-frequency = <50000000>;
+	cap-mmc-highspeed;
+	vmmc-supply = <&reg_3p3v>;
+	vqmmc-supply = <&reg_1p8v>;
+	non-removable;
+};
+
+&pinctrl {
+	ephy_default: ephy_default {
+		mux {
+			function = "eth";
+			groups = "mdc_mdio", "ephy";
+		};
+
+		conf {
+			pins = "G2_TXEN", "G2_TXD0", "G2_TXD1", "G2_TXD2",
+			       "G2_TXD3", "G2_TXC", "G2_RXC", "G2_RXD0",
+			       "G2_RXD1", "G2_RXD2", "G2_RXD3", "G2_RXDV",
+			       "MDC", "MDIO";
+			drive-strength = <12>;
+			mediatek,tdsel = <5>;
+		};
+	};
+
+	mmc0_pins_default: mmc0default {
+		mux {
+			function = "msdc";
+			groups =  "msdc0";
+		};
+
+		conf-cmd-data {
+			pins = "MSDC0_CMD", "MSDC0_DAT0", "MSDC0_DAT1",
+			       "MSDC0_DAT2", "MSDC0_DAT3", "MSDC0_DAT4",
+			       "MSDC0_DAT5", "MSDC0_DAT6", "MSDC0_DAT7";
+			input-enable;
+			bias-pull-up;
+		};
+
+		conf-clk {
+			pins = "MSDC0_CLK";
+			bias-pull-down;
+		};
+
+		conf-rst {
+			pins = "MSDC0_RSTB";
+			bias-pull-up;
+		};
+	};
+
+	pcie_default: pcie-default {
+		mux {
+			function = "pcie";
+			groups =  "pcie0_0_perst", "pcie1_0_perst";
+		};
+	};
+
+	uart0_pins_a: uart0-default {
+		mux {
+			function = "uart";
+			groups =  "uart0_0_txd_rxd";
+		};
+	};
+
+	uart1_pins_a: uart1-default {
+		mux {
+			function = "uart";
+			groups =  "uart1_0_txd_rxd";
+		};
+	};
+
+	uart2_pins_a: uart2-default {
+		mux {
+			function = "uart";
+			groups =  "uart2_0_txd_rxd";
+		};
+	};
+
+	uart2_pins_b: uart2-alt {
+		mux {
+			function = "uart";
+			groups =  "uart2_1_txd_rxd";
+		};
+	};
+};
+
+&pcie {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pcie_default>;
+	status = "okay";
+
+	pcie@0,0 {
+		status = "okay";
+	};
+
+	pcie@1,0 {
+		status = "okay";
+	};
+};
+
+&pcie0_phy {
+	status = "okay";
+};
+
+&pcie1_phy {
+	status = "okay";
+};
+
+&uart0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart0_pins_a>;
+	status = "okay";
+};
+
+&uart1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart1_pins_a>;
+	status = "okay";
+};
+
+&uart2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart2_pins_b>;
+	status = "okay";
+};
diff --git a/arch/arm/dts/mt7629-rfb.dts b/arch/arm/dts/mt7629-rfb.dts
index bf84f76344..5cc7294de6 100644
--- a/arch/arm/dts/mt7629-rfb.dts
+++ b/arch/arm/dts/mt7629-rfb.dts
@@ -24,12 +24,14 @@
 
 &eth {
 	status = "okay";
-	mediatek,gmac-id = <1>;
-	phy-mode = "gmii";
-	phy-handle = <&phy0>;
-
-	phy0: ethernet-phy@0 {
-		reg = <0>;
+	mediatek,gmac-id = <0>;
+	phy-mode = "sgmii";
+	mediatek,switch = "mt7531";
+	reset-gpios = <&gpio 28 GPIO_ACTIVE_HIGH>;
+
+	fixed-link {
+		speed = <1000>;
+		full-duplex;
 	};
 };
 
diff --git a/arch/arm/dts/qcom-ipq4019.dtsi b/arch/arm/dts/qcom-ipq4019.dtsi
new file mode 100644
index 0000000000..5f78bc5ab9
--- /dev/null
+++ b/arch/arm/dts/qcom-ipq4019.dtsi
@@ -0,0 +1,79 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2019 Sartura Ltd.
+ *
+ * Author: Robert Marko <robert.marko@sartura.hr>
+ */
+
+ /dts-v1/;
+
+#include "skeleton.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/pinctrl-snapdragon.h>
+
+/ {
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	model = "Qualcomm Technologies, Inc. IPQ4019";
+	compatible = "qcom,ipq4019";
+
+	aliases {
+		serial0 = &blsp1_uart1;
+	};
+
+	reserved-memory {
+		#address-cells = <0x1>;
+		#size-cells = <0x1>;
+		ranges;
+
+		smem_mem: smem_region: smem@87e00000 {
+			reg = <0x87e00000 0x080000>;
+			no-map;
+		};
+
+		tz@87e80000 {
+			reg = <0x87e80000 0x180000>;
+			no-map;
+		};
+	};
+
+	soc: soc {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+		compatible = "simple-bus";
+
+		gcc: clock-controller@1800000 {
+			compatible = "qcom,gcc-ipq4019";
+			reg = <0x1800000 0x60000>;
+			#clock-cells = <1>;
+			#reset-cells = <1>;
+			u-boot,dm-pre-reloc;
+		};
+
+		pinctrl: qcom,tlmm@1000000 {
+			compatible = "qcom,tlmm-ipq4019";
+			reg = <0x1000000 0x300000>;
+			u-boot,dm-pre-reloc;
+		};
+
+		blsp1_uart1: serial@78af000 {
+			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
+			reg = <0x78af000 0x200>;
+			clock = <&gcc 26>;
+			bit-rate = <0xFF>;
+			status = "disabled";
+			u-boot,dm-pre-reloc;
+		};
+
+		soc_gpios: pinctrl@1000000 {
+			compatible = "qcom,ipq4019-pinctrl";
+			reg = <0x1000000 0x300000>;
+			gpio-controller;
+			gpio-count = <100>;
+			gpio-bank-name="soc";
+			#gpio-cells = <2>;
+		};
+	};
+};
diff --git a/arch/arm/dts/s5p4418-nanopi2.dts b/arch/arm/dts/s5p4418-nanopi2.dts
new file mode 100644
index 0000000000..4deaf10a1c
--- /dev/null
+++ b/arch/arm/dts/s5p4418-nanopi2.dts
@@ -0,0 +1,110 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2020 Stefan Bosch <stefan_b@posteo.net>
+ *
+ * (C) Copyright 2017 FriendlyElec Computer Tech. Co., Ltd.
+ * (http://www.friendlyarm.com)
+ *
+ * (C) Copyright 2016 Nexell
+ * Youngbok, Park <park@nexell.co.kr>
+ */
+
+/dts-v1/;
+#include "s5p4418.dtsi"
+
+/ {
+	model = "FriendlyElec boards based on Nexell s5p4418";
+	cpu-model = "S5p4418";
+
+	compatible = "friendlyelec,nanopi2",
+		     "nexell,s5p4418";
+
+	aliases {
+		mmc0 = "/mmc@c0069000";
+		mmc1 = "/mmc@c0062000";
+		i2c0 = "/i2c@c00a4000";
+		i2c1 = "/i2c@c00a5000";
+		i2c2 = "/i2c@c00a6000";
+	};
+
+	mmc0:mmc@c0062000 {
+		frequency = <50000000>;
+		drive_dly = <0x0>;
+		drive_shift = <0x03>;
+		sample_dly = <0x00>;
+		sample_shift = <0x02>;
+		mmcboost = <0>;
+		status = "okay";
+	};
+
+	mmc2:mmc@c0069000 {
+		frequency = <50000000>;
+		drive_dly = <0x0>;
+		drive_shift = <0x03>;
+		sample_dly = <0x00>;
+		sample_shift = <0x02>;
+		mmcboost = <0>;
+		status = "okay";
+	};
+
+	/* NanoPi2: Header "CON2", NanoPC-T2: EEPROM (MAC-Addr.) and Audio */
+	i2c0:i2c@c00a4000 {
+		status ="okay";
+	};
+
+	/* NanoPi2: Header "CON2" and HDMI, NanoPC-T2: HDMI */
+	i2c1:i2c@c00a5000 {
+		status ="okay";
+	};
+
+	/* NanoPi2: LCD interface, NanoPC-T2: LCD, LVDS and MIPI interfaces */
+	i2c2:i2c@c00a6000 {
+		status ="okay";
+	};
+
+	dp0:dp@c0102800 {
+		status = "okay";
+		module = <0>;
+		lcd-type = "lvds";
+
+		dp-device {
+			format = <0>;	/* 0:VESA, 1:JEIDA */
+		};
+
+		dp-sync {
+			h_active_len = <1024>;
+			h_front_porch = <84>;
+			h_back_porch = <84>;
+			h_sync_width = <88>;
+			h_sync_invert = <0>;
+			v_active_len = <600>;
+			v_front_porch = <10>;
+			v_back_porch = <10>;
+			v_sync_width = <20>;
+			v_sync_invert = <0>;
+		};
+
+		dp-ctrl {
+			clk_src_lv0 = <3>;
+			clk_div_lv0 = <16>;
+			clk_src_lv1 = <7>;
+			clk_div_lv1 = <1>;
+			out_format = <2>;
+		};
+
+		dp-planes {
+			layer_top {
+				screen_width = <1024>;
+				screen_height = <600>;
+				back_color = <0x0>;
+			};
+
+			layer_1 {	/* RGB 1 */
+				width = <1024>;
+				height = <600>;
+				format = <0x06530000>;
+				pixel_byte = <4>;
+			};
+		};
+	};
+};
diff --git a/arch/arm/dts/s5p4418-pinctrl.dtsi b/arch/arm/dts/s5p4418-pinctrl.dtsi
new file mode 100644
index 0000000000..a7e1c2c381
--- /dev/null
+++ b/arch/arm/dts/s5p4418-pinctrl.dtsi
@@ -0,0 +1,135 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Nexell's s5p6818 SoC pin-mux and pin-config device tree source
+ *
+ * (C) Copyright 2020 Stefan Bosch <stefan_b@posteo.net>
+ *
+ * Copyright (C) 2016  Nexell Co., Ltd.
+ *		http://www.nexell.co.kr
+ *
+ * Nexell's s5p6818 SoC pin-mux and pin-config options are listed as
+ * device tree nodes in this file.
+ */
+
+pinctrl@C0010000 {
+	/*
+	 * values for "pin-pull":
+	 *	pulldown resistor = 0
+	 *	pullup = 1
+	 *	no pullup/down = 2
+	 */
+
+	/* MMC */
+	mmc0_clk: mmc0-clk {
+		pins = "gpioa-29";
+		pin-function = <1>;
+		pin-pull = <2>;
+		pin-strength = <2>;
+	};
+
+	mmc0_cmd: mmc0-cmd {
+		pins = "gpioa-31";
+		pin-function = <1>;
+		pin-pull = <2>;
+		pin-strength = <1>;
+	};
+
+	mmc0_bus4: mmc0-bus-width4 {
+		pins = "gpiob-1, gpiob-3, gpiob-5, gpiob-7";
+		pin-function = <1>;
+		pin-pull = <2>;
+		pin-strength = <1>;
+	};
+
+	mmc1_clk: mmc1-clk {
+		pins = "gpiod-22";
+		pin-function = <1>;
+		pin-pull = <2>;
+		pin-strength = <2>;
+	};
+
+	mmc1_cmd: mmc1-cmd {
+		pins = "gpiod-23";
+		pin-function = <1>;
+		pin-pull = <2>;
+		pin-strength = <1>;
+	};
+
+	mmc1_bus4: mmc1-bus-width4 {
+		pins = "gpiod-24, gpiod-25, gpiod-26, gpiod-27";
+		pin-function = <1>;
+		pin-pull = <2>;
+		pin-strength = <1>;
+	};
+
+	mmc2_clk: mmc2-clk {
+		pins = "gpioc-18";
+		pin-function = <2>;
+		pin-pull = <2>;
+		pin-strength = <2>;
+	};
+
+	mmc2_cmd: mmc2-cmd {
+		pins = "gpioc-19";
+		pin-function = <2>;
+		pin-pull = <2>;
+		pin-strength = <1>;
+	};
+
+	mmc2_bus4: mmc2-bus-width4 {
+		pins = "gpioc-20, gpioc-21, gpioc-22, gpioc-23";
+		pin-function = <2>;
+		pin-pull = <2>;
+		pin-strength = <1>;
+	};
+
+	mmc2_bus8: mmc2-bus-width8 {
+		nexell,pins = "gpioe-21", "gpioe-22", "gpioe-23", "gpioe-24";
+		pin-function = <2>;
+		pin-pull = <2>;
+		pin-strength = <1>;
+	};
+
+	/* I2C */
+	i2c0_sda:i2c0-sda {
+		pins = "gpiod-3";
+		pin-function = <1>;
+		pin-pull = <2>;
+		pin-strength = <0>;
+	};
+
+	i2c0_scl:i2c0-scl {
+		pins = "gpiod-2";
+		pin-function = <1>;
+		pin-pull = <2>;
+		pin-strength = <0>;
+	};
+
+	i2c1_sda:i2c1-sda {
+		pins = "gpiod-5";
+		pin-function = <1>;
+		pin-pull = <2>;
+		pin-strength = <0>;
+	};
+
+	i2c1_scl:i2c1-scl {
+		pins = "gpiod-4";
+		pin-function = <1>;
+		pin-pull = <2>;
+		pin-strength = <0>;
+	};
+
+	i2c2_sda:i2c2-sda {
+		pins = "gpiod-7";
+		pin-function = <1>;
+		pin-pull = <2>;
+		pin-strength = <0>;
+	};
+
+	i2c2_scl:i2c2-scl {
+		pins = "gpiod-6";
+		pin-function = <1>;
+		pin-pull = <2>;
+		pin-strength = <0>;
+	};
+};
diff --git a/arch/arm/dts/s5p4418.dtsi b/arch/arm/dts/s5p4418.dtsi
new file mode 100644
index 0000000000..a4d1a1bd03
--- /dev/null
+++ b/arch/arm/dts/s5p4418.dtsi
@@ -0,0 +1,170 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2020 Stefan Bosch <stefan_b@posteo.net>
+ *
+ * (C) Copyright 2016 Nexell
+ * Youngbok, Park <park@nexell.co.kr>
+ *
+ */
+
+#include "skeleton.dtsi"
+
+/ {
+	#include "s5p4418-pinctrl.dtsi"
+
+	aliases {
+		mmc0 = &mmc0;
+		mmc1 = &mmc1;
+		mmc2 = &mmc2;
+		gmac = "/ethernet@c0060000";
+	};
+
+	mmc2:mmc@c0069000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "nexell,nexell-dwmmc";
+		reg = <0xc0069000 0x1000>;
+		bus-width = <4>;
+		index = <2>;
+		max-frequency = <50000000>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&mmc2_clk>, <&mmc2_cmd>, <&mmc2_bus4>;
+		status = "disabled";
+	};
+
+	mmc1:mmc@c0068000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "nexell,nexell-dwmmc";
+		reg = <0xc0068000 0x1000>;
+		bus-width = <4>;
+		index = <1>;
+		max-frequency = <50000000>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&mmc1_clk>, <&mmc1_cmd>, <&mmc1_bus4>;
+		status = "disabled";
+	};
+
+	mmc0:mmc@c0062000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "nexell,nexell-dwmmc";
+		reg = <0xc0062000 0x1000>;
+		bus-width = <4>;
+		index = <0>;
+		max-frequency = <50000000>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&mmc0_clk>, <&mmc0_cmd>, <&mmc0_bus4>;
+		status = "disabled";
+	};
+
+	i2c0:i2c@c00a4000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "nexell,s5pxx18-i2c";
+		reg = <0xc00a4000 0x100>;
+		clock-frequency = <100000>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&i2c0_sda>, <&i2c0_scl>;
+		status ="disabled";
+	};
+
+	i2c1:i2c@c00a5000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "nexell,s5pxx18-i2c";
+		reg = <0xc00a5000 0x100>;
+		clock-frequency = <100000>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&i2c1_sda>, <&i2c1_scl>;
+		status ="disabled";
+	};
+
+	i2c2:i2c@c00a6000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "nexell,s5pxx18-i2c";
+		reg = <0xc00a6000 0x100>;
+		clock-frequency = <100000>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&i2c2_sda>, <&i2c2_scl>;
+		status ="disabled";
+	};
+
+	dp0:dp@c0102800 {
+		compatible = "nexell,nexell-display";
+		reg = <0xc0102800 0x100>;
+		index = <0>;
+		u-boot,dm-pre-reloc;
+		status = "disabled";
+	};
+
+	dp1:dp@c0102c00 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "nexell,nexell-display";
+		reg = <0xc0102c00 0x100>;
+		index = <1>;
+		status = "disabled";
+	};
+
+	gpio_a:gpio@c001a000 {
+		compatible = "nexell,nexell-gpio";
+		reg = <0xc001a000 0x00000010>;
+		altr,gpio-bank-width = <32>;
+		gpio-bank-name = "gpio_a";
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	gpio_b:gpio@c001b000 {
+		compatible = "nexell,nexell-gpio";
+		reg = <0xc001b000 0x00000010>;
+		altr,gpio-bank-width = <32>;
+		gpio-bank-name = "gpio_b";
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	gpio_c:gpio@c001c000 {
+		compatible = "nexell,nexell-gpio";
+		reg = <0xc001c000 0x00000010>;
+		nexell,gpio-bank-width = <32>;
+		gpio-bank-name = "gpio_c";
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	gpio_d:gpio@c001d000 {
+		compatible = "nexell,nexell-gpio";
+		reg = <0xc001d000 0x00000010>;
+		nexell,gpio-bank-width = <32>;
+		gpio-bank-name = "gpio_d";
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	gpio_e:gpio@c001e000 {
+		compatible = "nexell,nexell-gpio";
+		reg = <0xc001e000 0x00000010>;
+		nexell,gpio-bank-width = <32>;
+		gpio-bank-name = "gpio_e";
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	gpio_alv:gpio@c0010800 {
+		compatible = "nexell,nexell-gpio";
+		reg = <0xc0010800 0x00000010>;
+		nexell,gpio-bank-width = <32>;
+		gpio-bank-name = "gpio_alv";
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	pinctrl@C0010000 {
+		compatible = "nexell,s5pxx18-pinctrl";
+		reg = <0xc0010000 0xf000>;
+		u-boot,dm-pre-reloc;
+	};
+};