diff options
| author | Kever Yang <kever.yang@rock-chips.com> | 2019-03-29 22:48:25 +0800 |
|---|---|---|
| committer | Kever Yang <kever.yang@rock-chips.com> | 2019-05-08 17:34:12 +0800 |
| commit | 4d9dd40d68e4d1fbe170ade90e36753ff259ffca (patch) | |
| tree | 06a07daf3c824522b9041a313a551bc7c7603008 /arch/arm/dts | |
| parent | 579a1684663c6c7d440aead9b16525ae72fca8c8 (diff) | |
rockchip: px5 update dts for spl/tpl
TPL need dmc to init ddr sdram, and emmc, boot-order.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Tested-by: Andy Yan <andy.yan@rock-chips.com>
Diffstat (limited to 'arch/arm/dts')
| -rw-r--r-- | arch/arm/dts/rk3368-px5-evb-u-boot.dtsi | 29 |
1 files changed, 29 insertions, 0 deletions
diff --git a/arch/arm/dts/rk3368-px5-evb-u-boot.dtsi b/arch/arm/dts/rk3368-px5-evb-u-boot.dtsi index 7495781454..18b841864c 100644 --- a/arch/arm/dts/rk3368-px5-evb-u-boot.dtsi +++ b/arch/arm/dts/rk3368-px5-evb-u-boot.dtsi @@ -2,6 +2,27 @@ /* * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH */ +/ { + chosen { + u-boot,spl-boot-order = &emmc; + }; +}; + +&dmc { + u-boot,dm-pre-reloc; + + /* + * PX5-evb(2GB) need to use CBRD mode, or else the dram is not correct + * See doc/device-tree-bindings/clock/rockchip,rk3368-dmc.txt for + * details on the 'rockchip,memory-schedule' property and how it + * affects the physical-address to device-address mapping. + */ + rockchip,memory-schedule = <DMC_MSCH_CBRD>; + rockchip,ddr-frequency = <800000000>; + rockchip,ddr-speed-bin = <DDR3_1600K>; + + status = "okay"; +}; &pinctrl { u-boot,dm-pre-reloc; @@ -20,6 +41,10 @@ u-boot,dm-pre-reloc; }; +&sgrf { + u-boot,dm-pre-reloc; +}; + &cru { u-boot,dm-pre-reloc; }; @@ -31,3 +56,7 @@ &uart4 { u-boot,dm-pre-reloc; }; + +&emmc { + u-boot,dm-pre-reloc; +}; |