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| author | Tom Rini <trini@konsulko.com> | 2015-04-28 20:48:43 -0400 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2015-04-28 20:48:43 -0400 |
| commit | 536266231a340c0c5e571e1012bf3f8fc835b251 (patch) | |
| tree | 0b0284f73aa8f9f5608fdbc74a238efc4f8d1d23 /arch/arm/dts | |
| parent | 4842c58990ac065c2d33b71e1a7fde48f336dac2 (diff) | |
| parent | e5c57eea4f4ac8c27343bde137b069ef816e69d7 (diff) | |
Merge branch 'master' of git://www.denx.de/git/u-boot-socfpga
Diffstat (limited to 'arch/arm/dts')
| -rw-r--r-- | arch/arm/dts/socfpga_arria5_socdk.dts | 24 | ||||
| -rw-r--r-- | arch/arm/dts/socfpga_cyclone5_socdk.dts | 24 |
2 files changed, 48 insertions, 0 deletions
diff --git a/arch/arm/dts/socfpga_arria5_socdk.dts b/arch/arm/dts/socfpga_arria5_socdk.dts index 4e529a15c3..1b86897872 100644 --- a/arch/arm/dts/socfpga_arria5_socdk.dts +++ b/arch/arm/dts/socfpga_arria5_socdk.dts @@ -25,6 +25,10 @@ * to be added to the gmac1 device tree blob. */ ethernet0 = &gmac1; + + spi0 = "/spi@ff705000"; /* QSPI */ + spi1 = "/spi@fff00000"; + spi2 = "/spi@fff01000"; }; regulator_3_3v: 3-3-v-regulator { @@ -72,3 +76,23 @@ &usb1 { status = "okay"; }; + +&qspi { + status = "okay"; + + flash0: n25q00@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "n25q00"; + reg = <0>; /* chip select */ + spi-max-frequency = <50000000>; + m25p,fast-read; + page-size = <256>; + block-size = <16>; /* 2^16, 64KB */ + read-delay = <4>; /* delay value in read data capture register */ + tshsl-ns = <50>; + tsd2d-ns = <50>; + tchsh-ns = <4>; + tslch-ns = <4>; + }; +}; diff --git a/arch/arm/dts/socfpga_cyclone5_socdk.dts b/arch/arm/dts/socfpga_cyclone5_socdk.dts index 8e1f88c2c7..0b300b92be 100644 --- a/arch/arm/dts/socfpga_cyclone5_socdk.dts +++ b/arch/arm/dts/socfpga_cyclone5_socdk.dts @@ -25,6 +25,10 @@ * to be added to the gmac1 device tree blob. */ ethernet0 = &gmac1; + + spi0 = "/spi@ff705000"; /* QSPI */ + spi1 = "/spi@fff00000"; + spi2 = "/spi@fff01000"; }; regulator_3_3v: 3-3-v-regulator { @@ -77,3 +81,23 @@ &usb1 { status = "okay"; }; + +&qspi { + status = "okay"; + + flash0: n25q00@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "n25q00"; + reg = <0>; /* chip select */ + spi-max-frequency = <50000000>; + m25p,fast-read; + page-size = <256>; + block-size = <16>; /* 2^16, 64KB */ + read-delay = <4>; /* delay value in read data capture register */ + tshsl-ns = <50>; + tsd2d-ns = <50>; + tchsh-ns = <4>; + tslch-ns = <4>; + }; +}; |