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| author | Marcel Ziswiler <marcel.ziswiler@toradex.com> | 2018-05-09 00:18:38 +0200 |
|---|---|---|
| committer | Tom Warren <twarren@nvidia.com> | 2018-05-10 16:34:30 -0700 |
| commit | 6ab8a2b0ee7541f6e44fd8dca8cbacd8b7f45e65 (patch) | |
| tree | 221839501d68c7c9334d929da329156226d85d07 /arch/arm/dts | |
| parent | f1333417e82c3275cb46fe230bcdabd5b5f95922 (diff) | |
apalis_t30: describe pcie ports
Add some more comments describing the various PCIe ports available.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Diffstat (limited to 'arch/arm/dts')
| -rw-r--r-- | arch/arm/dts/tegra30-apalis.dts | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/arch/arm/dts/tegra30-apalis.dts b/arch/arm/dts/tegra30-apalis.dts index 0b84dae215..0852d8dc53 100644 --- a/arch/arm/dts/tegra30-apalis.dts +++ b/arch/arm/dts/tegra30-apalis.dts @@ -43,16 +43,19 @@ vddio-pex-ctl-supply = <&sys_3v3_reg>; hvdd-pex-supply = <&sys_3v3_reg>; + /* Apalis Type Specific 4 Lane PCIe */ pci@1,0 { /* TS_DIFF1/2/3/4 left disabled */ nvidia,num-lanes = <4>; }; + /* Apalis PCIe */ pci@2,0 { /* PCIE1_RX/TX left disabled */ nvidia,num-lanes = <1>; }; + /* I210 Gigabit Ethernet Controller (On-module) */ pci@3,0 { status = "okay"; nvidia,num-lanes = <1>; |