diff options
| author | Michal Simek <michal.simek@xilinx.com> | 2020-02-26 11:11:38 +0100 |
|---|---|---|
| committer | Michal Simek <michal.simek@xilinx.com> | 2020-04-06 12:51:31 +0200 |
| commit | 7c49a6d08e6dbdcb004f9a1129b40b297a2ac2f2 (patch) | |
| tree | d0324f91a878f3ef11f7d1a61c63f29ab4bc2b54 /arch/arm/dts | |
| parent | 0f8defd8910ed1a64687f79507c8332b72844aee (diff) | |
ARM: zynq: Do not include full zynq-7000.dtsi to cse-nor configuration
There is no real need to include full DT when only some nodes are enough to
use. It will save some space.
Retested with FSBL for initial SoC setup. SPL didn't work.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Diffstat (limited to 'arch/arm/dts')
| -rw-r--r-- | arch/arm/dts/zynq-cse-nor.dts | 13 |
1 files changed, 3 insertions, 10 deletions
diff --git a/arch/arm/dts/zynq-cse-nor.dts b/arch/arm/dts/zynq-cse-nor.dts index 9710abadcf..4030851eb3 100644 --- a/arch/arm/dts/zynq-cse-nor.dts +++ b/arch/arm/dts/zynq-cse-nor.dts @@ -5,7 +5,6 @@ * Copyright (C) 2018 Xilinx, Inc. */ /dts-v1/; -#include "zynq-7000.dtsi" / { #address-cells = <1>; @@ -33,27 +32,21 @@ }; amba: amba { + u-boot,dm-pre-reloc; compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; - interrupt-parent = <&intc>; ranges; - intc: interrupt-controller@f8f01000 { - compatible = "arm,cortex-a9-gic"; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0xF8F01000 0x1000>, - <0xF8F00100 0x100>; - }; - slcr: slcr@f8000000 { + u-boot,dm-pre-reloc; #address-cells = <1>; #size-cells = <1>; compatible = "xlnx,zynq-slcr", "syscon", "simple-bus"; reg = <0xF8000000 0x1000>; ranges; clkc: clkc@100 { + u-boot,dm-pre-reloc; #clock-cells = <1>; compatible = "xlnx,ps7-clkc"; clock-output-names = "armpll", "ddrpll", |