diff options
| author | Ian Ray <ian.ray@ge.com> | 2019-01-31 16:21:14 +0200 |
|---|---|---|
| committer | Stefano Babic <sbabic@denx.de> | 2019-04-13 20:30:08 +0200 |
| commit | 8d8d3540eb544fa29167d74029f92a99b9a31eea (patch) | |
| tree | dcb3004cce1940e64d46852bd77afa569bc0a95a /arch/arm/dts | |
| parent | 06f2e030d00053a13a8a81f4a352fd1ca8fbb66c (diff) | |
board: ge: bx50v3: Enable CONFIG_DM_SPI, CONFIG_DM_SPI_FLASH
Use SPI flash device model, and remove SPI pin configuration code since
the pinctrl driver is used.
Signed-off-by: Ian Ray <ian.ray@ge.com>
Diffstat (limited to 'arch/arm/dts')
| -rw-r--r-- | arch/arm/dts/imx6q-bx50v3.dts | 27 |
1 files changed, 27 insertions, 0 deletions
diff --git a/arch/arm/dts/imx6q-bx50v3.dts b/arch/arm/dts/imx6q-bx50v3.dts index 0fff2195f9..deaec63509 100644 --- a/arch/arm/dts/imx6q-bx50v3.dts +++ b/arch/arm/dts/imx6q-bx50v3.dts @@ -8,6 +8,7 @@ /dts-v1/; #include "imx6q.dtsi" +#include <dt-bindings/gpio/gpio.h> / { model = "General Electric Bx50v3"; @@ -17,6 +18,16 @@ &iomuxc { pinctrl-names = "default"; + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 + MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 + MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 + /* SPI1 CS */ + MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x1b0b0 + >; + }; + pinctrl_usdhc3: usdhc3grp { fsl,pins = < MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 @@ -60,3 +71,19 @@ &usdhc4 { status = "disabled"; }; + +/* SPI NOR */ +&ecspi1 { + cs-gpios = <&gpio2 30 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + status = "okay"; + + flash: n25q032@0 { + compatible = "jedec,spi-nor"; + #address-cells = <1>; + #size-cells = <1>; + spi-max-frequency = <20000000>; + reg = <0>; + }; +}; |