diff options
| author | Weijie Gao <weijie.gao@mediatek.com> | 2018-12-20 16:12:55 +0800 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2019-01-14 17:43:18 -0500 |
| commit | 9d42b613a8f45fb8fc91c43a40b6e4723b56eb63 (patch) | |
| tree | 4569df04d8b972f33bee43d77a8ee644d39cc855 /arch/arm/dts | |
| parent | d9506a6fdd0269f86c7a1fe5bbee7191acc3d1c8 (diff) | |
arm: dts: add ethernet related node for MT7629 SoC
This patch adds ethernet gmac node for MT7629 with internal gigabit phy.
Signed-off-by: Mark Lee <Mark-MC.Lee@mediatek.com>
Diffstat (limited to 'arch/arm/dts')
| -rw-r--r-- | arch/arm/dts/mt7629-rfb.dts | 11 | ||||
| -rw-r--r-- | arch/arm/dts/mt7629.dtsi | 43 |
2 files changed, 54 insertions, 0 deletions
diff --git a/arch/arm/dts/mt7629-rfb.dts b/arch/arm/dts/mt7629-rfb.dts index a6d28a060f..95d10aa6d3 100644 --- a/arch/arm/dts/mt7629-rfb.dts +++ b/arch/arm/dts/mt7629-rfb.dts @@ -22,6 +22,17 @@ }; }; +ð { + status = "okay"; + mediatek,gmac-id = <1>; + phy-mode = "gmii"; + phy-handle = <&phy0>; + + phy0: ethernet-phy@0 { + reg = <0>; + }; +}; + &pinctrl { qspi_pins: qspi-pins { mux { diff --git a/arch/arm/dts/mt7629.dtsi b/arch/arm/dts/mt7629.dtsi index e6052bbdcf..c87115e0fe 100644 --- a/arch/arm/dts/mt7629.dtsi +++ b/arch/arm/dts/mt7629.dtsi @@ -10,6 +10,7 @@ #include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/power/mt7629-power.h> +#include <dt-bindings/reset/mtk-reset.h> #include "skeleton.dtsi" / { @@ -228,6 +229,48 @@ compatible = "mediatek,mt7629-ethsys", "syscon"; reg = <0x1b000000 0x1000>; #clock-cells = <1>; + #reset-cells = <1>; + }; + + eth: ethernet@1b100000 { + compatible = "mediatek,mt7629-eth", "syscon"; + reg = <0x1b100000 0x20000>; + clocks = <&topckgen CLK_TOP_ETH_SEL>, + <&topckgen CLK_TOP_F10M_REF_SEL>, + <ðsys CLK_ETH_ESW_EN>, + <ðsys CLK_ETH_GP0_EN>, + <ðsys CLK_ETH_GP1_EN>, + <ðsys CLK_ETH_GP2_EN>, + <ðsys CLK_ETH_FE_EN>, + <&sgmiisys0 CLK_SGMII_TX_EN>, + <&sgmiisys0 CLK_SGMII_RX_EN>, + <&sgmiisys0 CLK_SGMII_CDR_REF>, + <&sgmiisys0 CLK_SGMII_CDR_FB>, + <&sgmiisys1 CLK_SGMII_TX_EN>, + <&sgmiisys1 CLK_SGMII_RX_EN>, + <&sgmiisys1 CLK_SGMII_CDR_REF>, + <&sgmiisys1 CLK_SGMII_CDR_FB>, + <&apmixedsys CLK_APMIXED_SGMIPLL>, + <&apmixedsys CLK_APMIXED_ETH2PLL>; + clock-names = "ethif", "sgmiitop", "esw", "gp0", "gp1", "gp2", + "fe", "sgmii_tx250m", "sgmii_rx250m", + "sgmii_cdr_ref", "sgmii_cdr_fb", + "sgmii2_tx250m", "sgmii2_rx250m", + "sgmii2_cdr_ref", "sgmii2_cdr_fb", + "sgmii_ck", "eth2pll"; + assigned-clocks = <&topckgen CLK_TOP_ETH_SEL>, + <&topckgen CLK_TOP_F10M_REF_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL1_D2>, + <&topckgen CLK_TOP_SGMIIPLL_D2>; + power-domains = <&scpsys MT7629_POWER_DOMAIN_ETHSYS>; + resets = <ðsys ETHSYS_FE_RST>; + reset-names = "fe"; + mediatek,ethsys = <ðsys>; + mediatek,sgmiisys = <&sgmiisys0>; + mediatek,infracfg = <&infracfg>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; }; sgmiisys0: syscon@1b128000 { |