diff options
| author | Marcel Ziswiler <marcel.ziswiler@toradex.com> | 2019-04-18 01:57:31 +0200 |
|---|---|---|
| committer | Stefano Babic <sbabic@denx.de> | 2019-04-25 19:18:46 +0200 |
| commit | d487351959427c730d4fa300cf18c98f5273837a (patch) | |
| tree | a30596e0e81fda4aacd6cf80be11e664ec2039b8 /arch/arm/dts | |
| parent | 7b69baea42b8c6431e9b92b0e79d860c40c27c51 (diff) | |
ARM: dts: colibri-imx6ull: add osc32k_32k_out pinctrl
Add GPIO1_IO03__OSC32K_32K_OUT pin muxing.
While at it also fix indentation of pinfunc header file.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Igor Opaniuk <igor.opaniuk@toradex.com>
Diffstat (limited to 'arch/arm/dts')
| -rw-r--r-- | arch/arm/dts/imx6ull-colibri.dts | 2 | ||||
| -rw-r--r-- | arch/arm/dts/imx6ull-pinfunc.h | 26 |
2 files changed, 16 insertions, 12 deletions
diff --git a/arch/arm/dts/imx6ull-colibri.dts b/arch/arm/dts/imx6ull-colibri.dts index f05c72eb2c..84f70deaa1 100644 --- a/arch/arm/dts/imx6ull-colibri.dts +++ b/arch/arm/dts/imx6ull-colibri.dts @@ -524,6 +524,8 @@ MX6UL_PAD_CSI_DATA03__USDHC2_DATA3 0x17059 MX6UL_PAD_CSI_HSYNC__USDHC2_CMD 0x17059 MX6UL_PAD_CSI_VSYNC__USDHC2_CLK 0x17059 + + MX6UL_PAD_GPIO1_IO03__OSC32K_32K_OUT 0x14 >; }; }; diff --git a/arch/arm/dts/imx6ull-pinfunc.h b/arch/arm/dts/imx6ull-pinfunc.h index fca003680b..7770ed39f6 100644 --- a/arch/arm/dts/imx6ull-pinfunc.h +++ b/arch/arm/dts/imx6ull-pinfunc.h @@ -14,6 +14,8 @@ * The pin function ID is a tuple of * <mux_reg conf_reg input_reg mux_mode input_val> */ +#define MX6UL_PAD_GPIO1_IO03__OSC32K_32K_OUT 0x0068 0x02f4 0x0000 0x3 0x0 + #define MX6UL_PAD_ENET2_RX_DATA0__EPDC_SDDO08 0x00E4 0x0370 0x0000 0x9 0x0 #define MX6UL_PAD_ENET2_RX_DATA1__EPDC_SDDO09 0x00E8 0x0374 0x0000 0x9 0x0 #define MX6UL_PAD_ENET2_RX_EN__EPDC_SDDO10 0x00EC 0x0378 0x0000 0x9 0x0 @@ -41,17 +43,17 @@ #define MX6UL_PAD_LCD_DATA17__EPDC_GDSP 0x015C 0x03E8 0x0000 0x9 0x0 #define MX6UL_PAD_LCD_DATA21__EPDC_SDCE1 0x016C 0x03F8 0x0000 0x9 0x0 -#define MX6UL_PAD_CSI_MCLK__ESAI_TX3_RX2 0x01D4 0x0460 0x0000 0x9 0x0 -#define MX6UL_PAD_CSI_PIXCLK__ESAI_TX2_RX3 0x01D8 0x0464 0x0000 0x9 0x0 -#define MX6UL_PAD_CSI_VSYNC__ESAI_TX4_RX1 0x01DC 0x0468 0x0000 0x9 0x0 -#define MX6UL_PAD_CSI_HSYNC__ESAI_TX1 0x01E0 0x046C 0x0000 0x9 0x0 -#define MX6UL_PAD_CSI_DATA00__ESAI_TX_HF_CLK 0x01E4 0x0470 0x0000 0x9 0x0 -#define MX6UL_PAD_CSI_DATA01__ESAI_RX_HF_CLK 0x01E8 0x0474 0x0000 0x9 0x0 -#define MX6UL_PAD_CSI_DATA02__ESAI_RX_FS 0x01EC 0x0478 0x0000 0x9 0x0 -#define MX6UL_PAD_CSI_DATA03__ESAI_RX_CLK 0x01F0 0x047C 0x0000 0x9 0x0 -#define MX6UL_PAD_CSI_DATA04__ESAI_TX_FS 0x01F4 0x0480 0x0000 0x9 0x0 -#define MX6UL_PAD_CSI_DATA05__ESAI_TX_CLK 0x01F8 0x0484 0x0000 0x9 0x0 -#define MX6UL_PAD_CSI_DATA06__ESAI_TX5_RX0 0x01FC 0x0488 0x0000 0x9 0x0 -#define MX6UL_PAD_CSI_DATA07__ESAI_T0 0x0200 0x048C 0x0000 0x9 0x0 +#define MX6UL_PAD_CSI_MCLK__ESAI_TX3_RX2 0x01D4 0x0460 0x0000 0x9 0x0 +#define MX6UL_PAD_CSI_PIXCLK__ESAI_TX2_RX3 0x01D8 0x0464 0x0000 0x9 0x0 +#define MX6UL_PAD_CSI_VSYNC__ESAI_TX4_RX1 0x01DC 0x0468 0x0000 0x9 0x0 +#define MX6UL_PAD_CSI_HSYNC__ESAI_TX1 0x01E0 0x046C 0x0000 0x9 0x0 +#define MX6UL_PAD_CSI_DATA00__ESAI_TX_HF_CLK 0x01E4 0x0470 0x0000 0x9 0x0 +#define MX6UL_PAD_CSI_DATA01__ESAI_RX_HF_CLK 0x01E8 0x0474 0x0000 0x9 0x0 +#define MX6UL_PAD_CSI_DATA02__ESAI_RX_FS 0x01EC 0x0478 0x0000 0x9 0x0 +#define MX6UL_PAD_CSI_DATA03__ESAI_RX_CLK 0x01F0 0x047C 0x0000 0x9 0x0 +#define MX6UL_PAD_CSI_DATA04__ESAI_TX_FS 0x01F4 0x0480 0x0000 0x9 0x0 +#define MX6UL_PAD_CSI_DATA05__ESAI_TX_CLK 0x01F8 0x0484 0x0000 0x9 0x0 +#define MX6UL_PAD_CSI_DATA06__ESAI_TX5_RX0 0x01FC 0x0488 0x0000 0x9 0x0 +#define MX6UL_PAD_CSI_DATA07__ESAI_T0 0x0200 0x048C 0x0000 0x9 0x0 #endif /* __DTS_IMX6ULL_PINFUNC_H */ |