diff options
| author | Matt Porter <mporter@ti.com> | 2013-03-15 10:07:03 +0000 |
|---|---|---|
| committer | Tom Rini <trini@ti.com> | 2013-03-24 12:49:11 -0400 |
| commit | 3ba65f97cbedb39fb486f42f8daa9b9e0d36705a (patch) | |
| tree | 0349f033250c48a61c82a6c3bc5bf85ad220c6c1 /arch/arm/include/asm/arch-am33xx/hardware.h | |
| parent | 81df2bab46d3bed319e21571c68db8e0a048bbfd (diff) | |
am33xx: refactor emif4/ddr to support multiple EMIF instances
The AM33xx emif4/ddr support closely matches what is need to support
TI814x except that TI814x has two EMIF instances. Refactor all the
emif4 helper calls and the config_ddr() init function to use an
additional instance number argument.
Signed-off-by: Matt Porter <mporter@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
Diffstat (limited to 'arch/arm/include/asm/arch-am33xx/hardware.h')
| -rw-r--r-- | arch/arm/include/asm/arch-am33xx/hardware.h | 13 |
1 files changed, 9 insertions, 4 deletions
diff --git a/arch/arm/include/asm/arch-am33xx/hardware.h b/arch/arm/include/asm/arch-am33xx/hardware.h index 7016e25a41..24a9b8d2d4 100644 --- a/arch/arm/include/asm/arch-am33xx/hardware.h +++ b/arch/arm/include/asm/arch-am33xx/hardware.h @@ -3,7 +3,7 @@ * * hardware specific header * - * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ + * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/ * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -20,6 +20,11 @@ #define __AM33XX_HARDWARE_H #include <asm/arch/omap.h> +#ifdef CONFIG_AM33XX +#include <asm/arch/hardware_am33xx.h> +#elif defined(CONFIG_TI814X) +#include <asm/arch/hardware_ti814x.h> +#endif /* Module base addresses */ #define UART0_BASE 0x44E09000 @@ -66,13 +71,13 @@ #define PRM_DEVICE 0x44E00F00 /* VTP Base address */ -#define VTP0_CTRL_ADDR 0x44E10E0C +#define VTP1_CTRL_ADDR 0x48140E10 /* DDR Base address */ #define DDR_CTRL_ADDR 0x44E10E04 #define DDR_CONTROL_BASE_ADDR 0x44E11404 -#define DDR_PHY_BASE_ADDR 0x44E12000 -#define DDR_PHY_BASE_ADDR2 0x44E120A4 +#define DDR_PHY_CMD_ADDR2 0x47C0C800 +#define DDR_PHY_DATA_ADDR2 0x47C0C8C8 /* UART */ #define DEFAULT_UART_BASE UART0_BASE |