diff options
| author | Steve Rae <srae@broadcom.com> | 2016-06-02 15:10:56 -0700 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2016-06-13 08:56:02 -0400 |
| commit | 43486e4cd094eabdd514ed7a2376ca55655e506f (patch) | |
| tree | 1cd8a75a92492366e98fe83343c946036a2d1245 /arch/arm/include/asm/arch-bcm235xx | |
| parent | 1e031249a53e38d9b8290fa99106477c231bf2dd (diff) | |
board: arm:: Add support for Broadcom BCM23550
Add support for the Broadcom BCM23550 board.
Signed-off-by: Steve Rae <srae@broadcom.com>
Diffstat (limited to 'arch/arm/include/asm/arch-bcm235xx')
| -rw-r--r-- | arch/arm/include/asm/arch-bcm235xx/gpio.h | 15 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-bcm235xx/sysmap.h | 31 |
2 files changed, 46 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-bcm235xx/gpio.h b/arch/arm/include/asm/arch-bcm235xx/gpio.h new file mode 100644 index 0000000000..da31f98710 --- /dev/null +++ b/arch/arm/include/asm/arch-bcm235xx/gpio.h @@ -0,0 +1,15 @@ +/* + * Copyright 2013 Broadcom Corporation. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ARCH_BCM235XX_GPIO_H +#define __ARCH_BCM235XX_GPIO_H + +/* + * Empty file - cmd_gpio.c requires this. The implementation + * is in drivers/gpio/kona_gpio.c instead of inlined here. + */ + +#endif diff --git a/arch/arm/include/asm/arch-bcm235xx/sysmap.h b/arch/arm/include/asm/arch-bcm235xx/sysmap.h new file mode 100644 index 0000000000..90eb2ff577 --- /dev/null +++ b/arch/arm/include/asm/arch-bcm235xx/sysmap.h @@ -0,0 +1,31 @@ +/* + * Copyright 2013 Broadcom Corporation. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ARCH_BCM235XX_SYSMAP_H + +#define BSC1_BASE_ADDR 0x3e016000 +#define BSC2_BASE_ADDR 0x3e017000 +#define BSC3_BASE_ADDR 0x3e018000 +#define GPIO2_BASE_ADDR 0x35003000 +#define HSOTG_BASE_ADDR 0x3f120000 +#define HSOTG_CTRL_BASE_ADDR 0x3f130000 +#define KONA_MST_CLK_BASE_ADDR 0x3f001000 +#define KONA_SLV_CLK_BASE_ADDR 0x3e011000 +#define PMU_BSC_BASE_ADDR 0x3500d000 +#define SDIO1_BASE_ADDR 0x3f180000 +#define SDIO2_BASE_ADDR 0x3f190000 +#define SDIO3_BASE_ADDR 0x3f1a0000 +#define SDIO4_BASE_ADDR 0x3f1b0000 +#define TIMER_BASE_ADDR 0x3e00d000 + +#define HSOTG_DCTL_OFFSET 0x00000804 +#define HSOTG_DCTL_SFTDISCON_MASK 0x00000002 + +#define HSOTG_CTRL_PHY_P1CTL_OFFSET 0x00000008 +#define HSOTG_CTRL_PHY_P1CTL_SOFT_RESET_MASK 0x00000002 +#define HSOTG_CTRL_PHY_P1CTL_NON_DRIVING_MASK 0x00000001 + +#endif |